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/linux-6.12.1/drivers/gpu/drm/i915/soc/
Dintel_pch.c10 /* Map PCH device id to PCH type, or PCH_NONE if unknown. */
16 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n"); in intel_pch_type()
20 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n"); in intel_pch_type()
25 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n"); in intel_pch_type()
31 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n"); in intel_pch_type()
38 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint LP PCH\n"); in intel_pch_type()
45 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint PCH\n"); in intel_pch_type()
53 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n"); in intel_pch_type()
61 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n"); in intel_pch_type()
66 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n"); in intel_pch_type()
[all …]
Dintel_pch.h13 * If the new PCH comes with a south display engine that is not
15 * end. Instead, add it right after its "parent" PCH.
18 PCH_NOP = -1, /* PCH without south display */
19 PCH_NONE = 0, /* No PCH present */
20 PCH_IBX, /* Ibexpeak PCH */
21 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
22 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
23 PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
24 PCH_CNP, /* Cannon/Comet Lake PCH */
25 PCH_ICP, /* Ice Lake/Jasper Lake PCH */
[all …]
/linux-6.12.1/drivers/net/ppp/
Dppp_generic.c264 static void ppp_channel_push(struct channel *pch);
266 struct channel *pch);
273 struct channel *pch);
288 static int ppp_connect_channel(struct channel *pch, int unit);
289 static int ppp_disconnect_channel(struct channel *pch);
290 static void ppp_destroy_channel(struct channel *pch);
641 static int ppp_bridge_channels(struct channel *pch, struct channel *pchb) in ppp_bridge_channels() argument
643 write_lock_bh(&pch->upl); in ppp_bridge_channels()
644 if (pch->ppp || in ppp_bridge_channels()
645 rcu_dereference_protected(pch->bridge, lockdep_is_held(&pch->upl))) { in ppp_bridge_channels()
[all …]
/linux-6.12.1/drivers/dma/
Dpl330.c1559 struct dma_pl330_chan *pch; in dma_pl330_rqcb() local
1565 pch = desc->pchan; in dma_pl330_rqcb()
1568 if (!pch) in dma_pl330_rqcb()
1571 spin_lock_irqsave(&pch->lock, flags); in dma_pl330_rqcb()
1575 spin_unlock_irqrestore(&pch->lock, flags); in dma_pl330_rqcb()
1577 tasklet_schedule(&pch->task); in dma_pl330_rqcb()
2042 static inline void fill_queue(struct dma_pl330_chan *pch) in fill_queue() argument
2047 list_for_each_entry(desc, &pch->work_list, node) { in fill_queue()
2053 ret = pl330_submit_req(pch->thread, desc); in fill_queue()
2062 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", in fill_queue()
[all …]
Dsa11x0-dma.c331 unsigned pch, pch_alloc = 0; in sa11x0_dma_tasklet() local
353 for (pch = 0; pch < NR_PHY_CHAN; pch++) { in sa11x0_dma_tasklet()
354 p = &d->phy[pch]; in sa11x0_dma_tasklet()
361 pch_alloc |= 1 << pch; in sa11x0_dma_tasklet()
366 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc); in sa11x0_dma_tasklet()
371 for (pch = 0; pch < NR_PHY_CHAN; pch++) { in sa11x0_dma_tasklet()
372 if (pch_alloc & (1 << pch)) { in sa11x0_dma_tasklet()
373 p = &d->phy[pch]; in sa11x0_dma_tasklet()
990 unsigned pch; in sa11x0_dma_remove() local
995 for (pch = 0; pch < NR_PHY_CHAN; pch++) in sa11x0_dma_remove()
[all …]
/linux-6.12.1/Documentation/arch/loongarch/
Dirq-chip-model.rst11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
43 | PCH-PIC | | PCH-MSI |
48 | PCH-LPC | | Devices | | Devices |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
75 | PCH-PIC | | PCH-MSI |
80 | PCH-LPC | | Devices | | Devices |
92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
[all …]
/linux-6.12.1/Documentation/translations/zh_CN/arch/loongarch/
Dirq-chip-model.rst15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
46 | PCH-PIC | | PCH-MSI |
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然后被EIOINTC统一收集，再直接到达CPUINTC::
77 | PCH-PIC | | PCH-MSI |
82 | PCH-LPC | | Devices | | Devices |
94 CPU串口（UARTs）中断发送到LIOINTC，PCH-MSI中断发送到AVECINTC，而后通过AVECINTC直接
[all …]
/linux-6.12.1/Documentation/translations/zh_TW/arch/loongarch/
Dirq-chip-model.rst15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片組的主中
16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
28 PCH-LPC/PCH-MSI，然後被HTVECINTC統一收集，再發送到LIOINTC，最後到達CPUINTC::
46 | PCH-PIC | | PCH-MSI |
51 | PCH-LPC | | Devices | | Devices |
64 PCH-LPC/PCH-MSI，然後被EIOINTC統一收集，再直接到達CPUINTC::
77 | PCH-PIC | | PCH-MSI |
82 | PCH-LPC | | Devices | | Devices |
117 PCH-PIC::
[all …]
/linux-6.12.1/drivers/pinctrl/intel/
DKconfig28 Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
29 provides an interface that allows configuring of PCH pins and
46 of Intel PCH pins and using them as GPIOs. Currently the following
56 of Intel Alder Lake PCH pins and using them as GPIOs.
66 tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
70 of Intel Cannon Lake PCH pins and using them as GPIOs.
77 of Intel Cedar Fork PCH pins and using them as GPIOs.
108 tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
112 of Intel Ice Lake PCH pins and using them as GPIOs.
115 tristate "Intel Jasper Lake PCH pinctrl and GPIO driver"
[all …]
/linux-6.12.1/Documentation/i2c/busses/
Di2c-i801.rst21 * Intel 5/3400 Series (PCH)
22 * Intel 6 Series (PCH)
23 * Intel Patsburg (PCH)
24 * Intel DH89xxCC (PCH)
25 * Intel Panther Point (PCH)
26 * Intel Lynx Point (PCH)
28 * Intel Wellsburg (PCH)
29 * Intel Coleto Creek (PCH)
30 * Intel Wildcat Point (PCH)
33 * Intel Sunrise Point (PCH)
[all …]
/linux-6.12.1/drivers/thermal/intel/
Dintel_pch_thermal.c2 /* intel_pch_thermal.c - Intel PCH Thermal driver
21 /* Intel PCH thermal Device IDs */
22 #define PCH_THERMAL_DID_HSW_1 0x9C24 /* Haswell PCH */
23 #define PCH_THERMAL_DID_HSW_2 0x8C24 /* Haswell PCH */
25 #define PCH_THERMAL_DID_SKL 0x9D31 /* Skylake PCH */
26 #define PCH_THERMAL_DID_SKL_H 0xA131 /* Skylake PCH 100 series */
27 #define PCH_THERMAL_DID_CNL 0x9Df9 /* CNL PCH */
28 #define PCH_THERMAL_DID_CNL_H 0xA379 /* CNL-H PCH */
29 #define PCH_THERMAL_DID_CNL_LP 0x02F9 /* CNL-LP PCH */
30 #define PCH_THERMAL_DID_CML_H 0X06F9 /* CML-H PCH */
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_fifo_underrun.c55 * The code also supports underrun detection on the PCH transcoder.
252 drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n", in cpt_check_pch_fifo_underruns()
276 "uncleared pch fifo underrun on pch transcoder %c\n", in cpt_set_fifo_underrun_reporting()
337 * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
339 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
342 * This function makes us disable or enable PCH fifo underruns for a specific
343 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
344 * underrun reporting for one transcoder may also disable all the other PCH
360 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT in intel_set_pch_fifo_underrun_reporting()
361 * has only one pch transcoder A that all pipes can use. To avoid racy in intel_set_pch_fifo_underrun_reporting()
[all …]
Dintel_pch_display.c48 "PCH DP %c enabled on transcoder %c, should be disabled\n", in assert_pch_dp_disabled()
53 "IBX PCH DP %c still using transcoder B\n", in assert_pch_dp_disabled()
67 "PCH HDMI %c enabled on transcoder %c, should be disabled\n", in assert_pch_hdmi_disabled()
72 "IBX PCH HDMI %c still using transcoder B\n", in assert_pch_hdmi_disabled()
87 "PCH VGA enabled on transcoder %c, should be disabled\n", in assert_pch_ports_disabled()
92 "PCH LVDS enabled on transcoder %c, should be disabled\n", in assert_pch_ports_disabled()
95 /* PCH SDVOB multiplex with HDMIB */ in assert_pch_ports_disabled()
155 * The BIOS may select transcoder B on some of the PCH in ibx_sanitize_pch_ports()
169 /* PCH SDVOB multiplex with HDMIB */ in ibx_sanitize_pch_ports()
251 /* Make sure PCH DPLL is enabled */ in ilk_enable_pch_transcoder()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,pch-msi.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
7 title: Loongson PCH MSI Controller
13 This interrupt controller is found in the Loongson LS7A family of PCH for
19 const: loongson,pch-msi-1.0
27 to PCH MSI.
35 to PCH MSI.
55 compatible = "loongson,pch-msi-1.0";
Dloongson,pch-pic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
7 title: Loongson PCH PIC Controller
13 This interrupt controller is found in the Loongson LS7A family of PCH for
19 const: loongson,pch-pic-1.0
27 to PCH PIC.
50 compatible = "loongson,pch-pic-1.0";
/linux-6.12.1/tools/bpf/bpftool/
Dperf.c159 const char *pch; in show_proc() local
168 pch = proc_de->d_name; in show_proc()
171 while (isdigit(*pch)) { in show_proc()
172 pid = pid * 10 + *pch - '0'; in show_proc()
173 pch++; in show_proc()
175 if (*pch != '\0') in show_proc()
188 pch = pid_fd_de->d_name; in show_proc()
191 while (isdigit(*pch)) { in show_proc()
192 fd = fd * 10 + *pch - '0'; in show_proc()
193 pch++; in show_proc()
[all …]
/linux-6.12.1/drivers/hwtracing/intel_th/
Dpci.c163 /* Kaby Lake PCH-H */
173 /* Lewisburg PCH */
178 /* Lewisburg PCH */
198 /* Cedar Fork PCH */
203 /* Ice Lake PCH */
213 /* Comet Lake PCH */
218 /* Comet Lake PCH-V */
238 /* Tiger Lake PCH */
243 /* Tiger Lake PCH-H */
248 /* Jasper Lake PCH */
[all …]
/linux-6.12.1/drivers/net/ethernet/oki-semi/pch_gbe/
DKconfig14 This is a gigabit ethernet driver for EG20T PCH.
15 EG20T PCH is the platform controller hub that is used in Intel's
16 general embedded platform. EG20T PCH has Gigabit Ethernet interface.
25 ML7223/ML7831 is completely compatible for Intel EG20T PCH.
/linux-6.12.1/drivers/i2c/busses/
Di2c-i801.c34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
[all …]
DKconfig109 tristate "Intel 82801 (ICH/PCH)"
132 5/3400 Series (PCH)
133 6 Series (PCH)
134 Patsburg (PCH)
135 DH89xxCC (PCH)
136 Panther Point (PCH)
137 Lynx Point (PCH)
139 Wellsburg (PCH)
140 Coleto Creek (PCH)
141 Wildcat Point (PCH)
[all …]
/linux-6.12.1/Documentation/PCI/
Dboot-interrupts.rst16 IO-APIC table entries), the messages are routed to the legacy PCH. This
23 PCH and mitigation within BIOS and the OS.
29 When in-band legacy INTx messages are forwarded to the PCH, they in turn
80 devices. IO-APIC is only in the PCH. Devices connected to the Core IO's
87 first identify and make use of a means to disable the routing to the PCH.
105 PCH - they are either converted into MSI via the integrated IO-APIC
119 disable) the redirection of the interrupt handler to the PCH interrupt
/linux-6.12.1/drivers/platform/x86/intel/pmc/
DKconfig21 - PCH IP Power Gating status
23 - MPHY/PLL gating status (Sunrisepoint PCH only)
24 - SLPS0 Debug registers (Cannonlake/Icelake PCH)
/linux-6.12.1/arch/mips/boot/dts/loongson/
Dloongson64c_4core_ls7a.dts6 #include "ls7a-pch.dtsi"
27 &pch {
29 compatible = "loongson,pch-msi-1.0";
Dloongson64g_4core_ls7a.dts6 #include "ls7a-pch.dtsi"
31 &pch {
33 compatible = "loongson,pch-msi-1.0";
/linux-6.12.1/drivers/acpi/dptf/
DKconfig33 tristate "PCH FIVR DPTF Participant"
37 (DPTF) PCH FIVR Participant device support. This driver allows to
38 switch the PCH FIVR (Fully Integrated Voltage Regulator) frequency.

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