arch/loongarch/irq-chip-model.rst

11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
43            | PCH-PIC | | PCH-MSI |
48      | PCH-LPC | | Devices | | Devices |
61 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
75           | PCH-PIC | | PCH-MSI |
80     | PCH-LPC | | Devices | | Devices |
92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
94 go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly::
107        | PCH-PIC |  | PCH-MSI |
112  | Devices | | PCH-LPC | | Devices |
147 PCH-PIC::
153 PCH-MSI::
159 PCH-LPC::
189     - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
191     - PCH-LPC is "LPC Interrupts" described in Section 24.3 of