| /linux-6.12.1/include/linux/mtd/ |
| D | nand.h | 19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
96 * struct nand_page_io_req - NAND I/O request object
107 * NAND device will automatically prepare the next one
109 * This object is used to pass per-page I/O requests to NAND sub-layers. This
111 * specific NAND layers can focus on translating these information into
138 * enum nand_ecc_engine_type - NAND ECC engine type
154 * enum nand_ecc_placement - NAND ECC bytes placement
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| /linux-6.12.1/drivers/mtd/nand/ |
| D | core.c | 10 #define pr_fmt(fmt) "nand: " fmt
13 #include <linux/mtd/nand.h>
17 * @nand: NAND device
22 bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_isbad() argument
27 if (nanddev_bbt_is_initialized(nand)) { in nanddev_isbad()
31 entry = nanddev_bbt_pos_to_entry(nand, pos); in nanddev_isbad()
32 status = nanddev_bbt_get_block_status(nand, entry); in nanddev_isbad()
35 if (nand->ops->isbad(nand, pos)) in nanddev_isbad()
40 nanddev_bbt_set_block_status(nand, entry, status); in nanddev_isbad()
50 return nand->ops->isbad(nand, pos); in nanddev_isbad()
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| D | ecc.c | 10 * This file describes the abstraction of any NAND ECC engine. It has been
15 * - external: The ECC engine is outside the NAND pipeline, typically this
17 * outside the NAND controller pipeline.
18 * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the
19 * controller's side. This is the case of most of the raw NAND
23 * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side.
24 * Some NAND chips can correct themselves the data.
44 * - read: Load data from the NAND chip
45 * - write: Store data in the NAND chip
97 #include <linux/mtd/nand.h>
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| D | ecc-sw-bch.c | 14 #include <linux/mtd/nand.h>
15 #include <linux/mtd/nand-ecc-sw-bch.h>
19 * @nand: NAND device
23 int nand_ecc_sw_bch_calculate(struct nand_device *nand, in nand_ecc_sw_bch_calculate() argument
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
42 * @nand: NAND device
49 int nand_ecc_sw_bch_correct(struct nand_device *nand, unsigned char *buf, in nand_ecc_sw_bch_correct() argument
52 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_correct()
53 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_correct()
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| D | bbt.c | 10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
17 * @nand: NAND device
23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
28 nand->bbt.cache = bitmap_zalloc(nblocks * bits_per_block, GFP_KERNEL); in nanddev_bbt_init()
29 if (!nand->bbt.cache) in nanddev_bbt_init()
38 * @nand: NAND device
42 void nanddev_bbt_cleanup(struct nand_device *nand) in nanddev_bbt_cleanup() argument
44 bitmap_free(nand->bbt.cache); in nanddev_bbt_cleanup()
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| /linux-6.12.1/drivers/mtd/nand/raw/ |
| D | Kconfig | 3 tristate "Raw/Parallel NAND Device Support"
8 NAND flash devices. For further information see
9 <http://www.linux-mtd.infradead.org/doc/nand.html>.
13 comment "Raw/parallel NAND flash controllers"
19 tristate "Denali NAND controller on Intel Moorestown"
23 Enable the driver for NAND flash on Intel Moorestown, using the
24 Denali NAND controller core.
27 tristate "Denali NAND controller as a DT device"
31 Enable the driver for NAND flash on platforms using a Denali NAND
35 tristate "Amstrad E3 NAND controller"
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| D | meson_nand.c | 3 * Amlogic Meson Nand Flash Controller Driver
101 /* nand flash controller delay 3 ns */
124 struct nand_chip nand; member
258 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) in to_meson_nand() argument
260 return container_of(nand, struct meson_nfc_nand_chip, nand); in to_meson_nand()
263 static void meson_nfc_select_chip(struct nand_chip *nand, int chip) in meson_nfc_select_chip() argument
265 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); in meson_nfc_select_chip()
266 struct meson_nfc *nfc = nand_get_controller_data(nand); in meson_nfc_select_chip()
306 static int meson_nfc_is_boot_page(struct nand_chip *nand, int page) in meson_nfc_is_boot_page() argument
308 const struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); in meson_nfc_is_boot_page()
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| D | nand_ids.c | 25 * Some incompatible NAND chips share device ID's and so must be
68 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
69 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
70 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
71 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
72 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
74 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
75 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
76 LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16),
77 LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16),
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| D | sunxi_nand.c | 161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
174 * @ecc_ctl: ECC_CTL register value for this NAND chip
181 * struct sunxi_nand_chip - stores NAND chip device related information
183 * @node: used to store NAND chips into a list
184 * @nand: base NAND chip structure
186 * @clk_rate: clk_rate required for this NAND chip
187 * @timing_cfg: TIMING_CFG register value for this NAND chip
188 * @timing_ctl: TIMING_CTL register value for this NAND chip
189 * @nsels: number of CS lines required by the NAND chip
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| D | Makefile | 3 obj-$(CONFIG_MTD_RAW_NAND) += nand.o
37 obj-$(CONFIG_MTD_NAND_TS72XX) += technologic-nand-controller.o
43 obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
55 obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o
56 obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o
57 obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o
58 obj-$(CONFIG_MTD_NAND_ROCKCHIP) += rockchip-nand-controller.o
59 obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o
60 obj-$(CONFIG_MTD_NAND_RENESAS) += renesas-nand-controller.o
62 nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
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| /linux-6.12.1/Documentation/devicetree/bindings/mtd/ |
| D | brcm,brcmnand.yaml | 7 title: Broadcom STB NAND Controller
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
27 -- Additional SoC-specific NAND controller properties --
29 The NAND controller is integrated differently on the variety of SoCs on which
31 bits with which to control the 8 exposed NAND interrupts, as well as hardware
35 interesting ways, sometimes with registers that lump multiple NAND-related
39 register resources within the NAND controller node above.
58 - description: BCMBCA SoC-specific NAND controller
60 - const: brcm,nand-bcm63138
65 - description: iProc SoC-specific NAND controller
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| D | marvell,nand-controller.yaml | 4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
7 title: Marvell NAND Flash Controller (NFC)
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
19 - marvell,ac5-nand-controller
20 - marvell,armada370-nand-controller
21 - marvell,pxa3xx-nand-controller
25 - marvell,armada-8k-nand
26 - marvell,armada370-nand
27 - marvell,pxa3xx-nand
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| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
5 - "nvidia,tegra20-nand"
11 - nand
15 - nand
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
29 - nand-bus-width : See nand-controller.yaml
30 - nand-on-flash-bbt: See nand-controller.yaml
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| D | denali,nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml#
7 title: Denali NAND controller
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
38 nand: controller core clock
42 - const: nand
53 nand: controller core reset
57 - const: nand
59 - const: nand
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| D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
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| D | qcom,nandc.yaml | 7 title: Qualcomm NAND controller
15 - qcom,ipq806x-nand
16 - qcom,ipq4019-nand
17 - qcom,ipq6018-nand
18 - qcom,ipq8074-nand
19 - qcom,sdx55-nand
38 the NAND controller on the given platform
44 the NAND controller on the given platform
47 "^nand@[a-f0-9]$":
49 $ref: raw-nand-chip.yaml
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| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
10 - #address-cells: shall be set to 1. Encode the nand CS.
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
23 Children nodes represent the available nand chips. Currently the driver can
24 only handle one NAND chip.
28 - nand-bus-width: see nand-controller.yaml
29 - nand-ecc-mode: see nand-controller.yaml
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| D | samsung-s3c2410.txt | 1 * Samsung S3C2410 and compatible NAND flash controller
5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
14 Child nodes representing the available nand chips.
17 - nand-ecc-mode : see nand-controller.yaml
18 - nand-on-flash-bbt : see nand-controller.yaml
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| D | gpmi-nand.yaml | 4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
13 The GPMI nand controller provides an interface to control the NAND
22 - fsl,imx23-gpmi-nand
23 - fsl,imx28-gpmi-nand
24 - fsl,imx6q-gpmi-nand
25 - fsl,imx6sx-gpmi-nand
26 - fsl,imx7d-gpmi-nand
27 - fsl,imx8qxp-gpmi-nand
30 - fsl,imx8mm-gpmi-nand
31 - fsl,imx8mn-gpmi-nand
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| D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
29 nand: nand@4020000 {
33 nand-bus-width = <8>;
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| D | fsmc-nand.txt | 2 NAND Interface
5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
43 compatible = "st,spear600-fsmc-nand";
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| D | davinci-nand.txt | 1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
22 for accessing the nand.
29 address for the chip select space the NAND Flash
35 address for the chip select space the NAND Flash
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
50 - nand-bus-width: buswidth 8 or 16. If not present 8.
52 - nand-on-flash-bbt: use flash based bad block table support. OOB
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| D | mediatek,mtk-nfc.yaml | 7 title: MediaTek(MTK) SoCs raw NAND FLASH controller (NFC)
42 "^nand@[a-f0-9]$":
43 $ref: raw-nand-chip.yaml#
48 nand-ecc-mode:
52 - $ref: nand-controller.yaml#
61 "^nand@[a-f0-9]$":
63 nand-ecc-step-size:
65 nand-ecc-strength:
76 "^nand@[a-f0-9]$":
78 nand-ecc-step-size:
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| /linux-6.12.1/drivers/mtd/nand/spi/ |
| D | core.c | 10 #define pr_fmt(fmt) "spi-nand: " fmt
53 struct nand_device *nand = spinand_to_nand(spinand); in spinand_get_cfg() local
56 spinand->cur_target >= nand->memorg.ntargets)) in spinand_get_cfg()
65 struct nand_device *nand = spinand_to_nand(spinand); in spinand_set_cfg() local
69 spinand->cur_target >= nand->memorg.ntargets)) in spinand_set_cfg()
109 * spinand_select_target() - Select a specific NAND target/die
119 struct nand_device *nand = spinand_to_nand(spinand); in spinand_select_target() local
122 if (WARN_ON(target >= nand->memorg.ntargets)) in spinand_select_target()
128 if (nand->memorg.ntargets == 1) { in spinand_select_target()
143 struct nand_device *nand = spinand_to_nand(spinand); in spinand_read_cfg() local
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| /linux-6.12.1/drivers/mtd/nand/raw/atmel/ |
| D | nand-controller.c | 13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
201 struct atmel_nand *nand);
203 int (*setup_interface)(struct atmel_nand *nand, int csline,
205 int (*exec_op)(struct atmel_nand *nand,
337 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); in atmel_nfc_wait()
462 "Failed to send NAND command (err = %d)!", in atmel_nfc_exec_op()
471 static void atmel_nand_data_in(struct atmel_nand *nand, void *buf, in atmel_nand_data_in() argument
476 nc = to_nand_controller(nand->base.controller); in atmel_nand_data_in()
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