| /linux-6.12.1/Documentation/devicetree/bindings/mux/ |
| D | mux-consumer.yaml | 4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
13 Mux controller consumers should specify a list of mux controllers that they
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
18 mux-ctrl-phandle : phandle to mux controller node
19 mux-ctrl-specifier : array of #mux-control-cells specifying the
20 given mux controller (controller specific)
22 Mux controller properties should be named "mux-controls". The exact meaning of
23 each mux controller property must be documented in the device tree binding for
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| D | mux-controller.yaml | 4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
13 A multiplexer (or mux) controller will have one, or several, consumer devices
14 that uses the mux controller. Thus, a mux controller can possibly control
16 multiplexer needed by each consumer, but a single mux controller can of course
19 A mux controller provides a number of states to its consumers, and the state
24 Mux controller nodes
27 Mux controller nodes must specify the number of cells used for the
28 specifier using the '#mux-control-cells' or '#mux-state-cells' property.
29 The value of '#mux-state-cells' will always be one greater than the value
30 of '#mux-control-cells'.
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| D | reg-mux.yaml | 4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
33 description: Each entry pair describes a single mux control.
39 - mux-reg-masks
40 - '#mux-control-cells'
46 /* The parent device of mux controller is not a syscon device. */
48 #include <dt-bindings/mux/mux.h>
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| D | adi,adg792a.txt | 5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
6 with a single mux controller controlling all three muxes), or <1> if
7 not (one mux controller for each mux).
8 * Standard mux-controller bindings as described in mux-controller.yaml
18 - idle-state : if present, array of states that the mux controllers will have
27 * Three independent mux controllers (of which one is used).
28 * Mux 0 is disconnected when idle, mux 1 idles in the previously
29 * selected state and mux 2 idles with signal B.
32 mux: mux-controller@50 {
35 #mux-control-cells = <1>;
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| D | gpio-mux.yaml | 4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
22 const: gpio-mux
24 mux-gpios:
28 '#mux-control-cells':
31 '#mux-state-cells':
39 - mux-gpios
42 - "#mux-control-cells"
44 - "#mux-state-cells"
52 mux: mux-controller {
53 compatible = "gpio-mux";
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| /linux-6.12.1/drivers/mux/ |
| D | core.c | 10 #define pr_fmt(fmt) "mux-core: " fmt
19 #include <linux/mux/consumer.h>
20 #include <linux/mux/driver.h>
32 * struct mux_state - Represents a mux controller state specific to a given
34 * @mux: Pointer to a mux controller.
35 * @state: State of the mux to be selected.
41 struct mux_control *mux; member
46 .name = "mux",
72 .name = "mux-chip",
77 * mux_chip_alloc() - Allocate a mux-chip.
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| /linux-6.12.1/drivers/clk/ti/ |
| D | mux.c | 23 struct clk_omap_mux *mux = to_clk_omap_mux(hw); in ti_clk_mux_get_parent() local
28 * FIXME need a mux-specific flag to determine if val is bitwise or in ti_clk_mux_get_parent()
34 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
35 val &= mux->mask; in ti_clk_mux_get_parent()
37 if (mux->table) { in ti_clk_mux_get_parent()
41 if (mux->table[i] == val) in ti_clk_mux_get_parent()
46 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) in ti_clk_mux_get_parent()
49 if (val && (mux->flags & CLK_MUX_INDEX_ONE)) in ti_clk_mux_get_parent()
60 struct clk_omap_mux *mux = to_clk_omap_mux(hw); in ti_clk_mux_set_parent() local
63 if (mux->table) { in ti_clk_mux_set_parent()
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mux.c | 18 #include "clk-mux.h"
35 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); in mtk_clk_mux_enable_setclr() local
38 if (mux->lock) in mtk_clk_mux_enable_setclr()
39 spin_lock_irqsave(mux->lock, flags); in mtk_clk_mux_enable_setclr()
41 __acquire(mux->lock); in mtk_clk_mux_enable_setclr()
43 regmap_write(mux->regmap, mux->data->clr_ofs, in mtk_clk_mux_enable_setclr()
44 BIT(mux->data->gate_shift)); in mtk_clk_mux_enable_setclr()
48 * not be effective yet. Set the update bit to ensure the mux gets in mtk_clk_mux_enable_setclr()
51 if (mux->reparent && mux->data->upd_shift >= 0) { in mtk_clk_mux_enable_setclr()
52 regmap_write(mux->regmap, mux->data->upd_ofs, in mtk_clk_mux_enable_setclr()
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| D | clk-cpumux.c | 33 struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw); in clk_cpumux_get_parent() local
36 regmap_read(mux->regmap, mux->reg, &val); in clk_cpumux_get_parent()
38 val >>= mux->shift; in clk_cpumux_get_parent()
39 val &= mux->mask; in clk_cpumux_get_parent()
46 struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw); in clk_cpumux_set_parent() local
49 val = index << mux->shift; in clk_cpumux_set_parent()
50 mask = mux->mask << mux->shift; in clk_cpumux_set_parent()
52 return regmap_update_bits(mux->regmap, mux->reg, mask, val); in clk_cpumux_set_parent()
62 mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux, in mtk_clk_register_cpumux() argument
73 init.name = mux->name; in mtk_clk_register_cpumux()
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| /linux-6.12.1/drivers/iio/multiplexer/ |
| D | iio-mux.c | 16 #include <linux/mux/consumer.h>
29 struct mux { struct
39 static int iio_mux_select(struct mux *mux, int idx) in iio_mux_select() argument
41 struct mux_child *child = &mux->child[idx]; in iio_mux_select()
42 struct iio_chan_spec const *chan = &mux->chan[idx]; in iio_mux_select()
46 ret = mux_control_select_delay(mux->control, chan->channel, in iio_mux_select()
47 mux->delay_us); in iio_mux_select()
49 mux->cached_state = -1; in iio_mux_select()
53 if (mux->cached_state == chan->channel) in iio_mux_select()
66 ret = iio_write_channel_ext_info(mux->parent, attr, in iio_mux_select()
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| /linux-6.12.1/drivers/i2c/muxes/ |
| D | i2c-mux-reg.c | 10 #include <linux/i2c-mux.h>
15 #include <linux/platform_data/i2c-mux-reg.h>
23 static int i2c_mux_reg_set(const struct regmux *mux, unsigned int chan_id) in i2c_mux_reg_set() argument
25 if (!mux->data.reg) in i2c_mux_reg_set()
34 switch (mux->data.reg_size) { in i2c_mux_reg_set()
36 if (mux->data.little_endian) in i2c_mux_reg_set()
37 iowrite32(chan_id, mux->data.reg); in i2c_mux_reg_set()
39 iowrite32be(chan_id, mux->data.reg); in i2c_mux_reg_set()
40 if (!mux->data.write_only) in i2c_mux_reg_set()
41 ioread32(mux->data.reg); in i2c_mux_reg_set()
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| D | i2c-mux-gpio.c | 13 #include <linux/i2c-mux.h>
16 #include <linux/platform_data/i2c-mux-gpio.h>
26 static void i2c_mux_gpio_set(const struct gpiomux *mux, unsigned int val) in i2c_mux_gpio_set() argument
32 gpiod_set_array_value_cansleep(mux->ngpios, mux->gpios, NULL, values); in i2c_mux_gpio_set()
37 struct gpiomux *mux = i2c_mux_priv(muxc); in i2c_mux_gpio_select() local
39 i2c_mux_gpio_set(mux, chan); in i2c_mux_gpio_select()
41 if (mux->data.settle_time) in i2c_mux_gpio_select()
42 fsleep(mux->data.settle_time); in i2c_mux_gpio_select()
49 struct gpiomux *mux = i2c_mux_priv(muxc); in i2c_mux_gpio_deselect() local
51 i2c_mux_gpio_set(mux, mux->data.idle); in i2c_mux_gpio_deselect()
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ring_mux.c | 43 static inline struct amdgpu_mux_entry *amdgpu_ring_mux_sw_entry(struct amdgpu_ring_mux *mux, in amdgpu_ring_mux_sw_entry() argument
46 return ring->entry_index < mux->ring_entry_size ? in amdgpu_ring_mux_sw_entry()
47 &mux->ring_entry[ring->entry_index] : NULL; in amdgpu_ring_mux_sw_entry()
51 static void amdgpu_ring_mux_copy_pkt_from_sw_ring(struct amdgpu_ring_mux *mux, in amdgpu_ring_mux_copy_pkt_from_sw_ring() argument
56 struct amdgpu_ring *real_ring = mux->real_ring; in amdgpu_ring_mux_copy_pkt_from_sw_ring()
76 static void amdgpu_mux_resubmit_chunks(struct amdgpu_ring_mux *mux) in amdgpu_mux_resubmit_chunks() argument
84 if (!mux->s_resubmit) in amdgpu_mux_resubmit_chunks()
87 for (i = 0; i < mux->num_ring_entries; i++) { in amdgpu_mux_resubmit_chunks()
88 if (mux->ring_entry[i].ring->hw_prio <= AMDGPU_RING_PRIO_DEFAULT) { in amdgpu_mux_resubmit_chunks()
89 e = &mux->ring_entry[i]; in amdgpu_mux_resubmit_chunks()
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| /linux-6.12.1/sound/soc/codecs/ |
| D | rt5665.c | 955 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
958 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
961 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
964 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
967 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
970 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
973 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
976 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
1879 "DD Mux", "ADC"
1947 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
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| D | tas5086.c | 550 /* Input mux controls */
575 /* Output mux controls */
577 { "Channel 1 Mux", "Channel 2 Mux", "Channel 3 Mux",
578 "Channel 4 Mux", "Channel 5 Mux", "Channel 6 Mux" };
615 SND_SOC_DAPM_MUX("Channel 1 Mux", SND_SOC_NOPM, 0, 0,
617 SND_SOC_DAPM_MUX("Channel 2 Mux", SND_SOC_NOPM, 0, 0,
619 SND_SOC_DAPM_MUX("Channel 3 Mux", SND_SOC_NOPM, 0, 0,
621 SND_SOC_DAPM_MUX("Channel 4 Mux", SND_SOC_NOPM, 0, 0,
623 SND_SOC_DAPM_MUX("Channel 5 Mux", SND_SOC_NOPM, 0, 0,
625 SND_SOC_DAPM_MUX("Channel 6 Mux", SND_SOC_NOPM, 0, 0,
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| D | rt5677.c | 1737 /* Mux */
2884 /* ADC Mux */
2885 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2887 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2889 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2891 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
2893 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
2895 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
2897 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
2899 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
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| /linux-6.12.1/include/linux/mux/ |
| D | driver.h | 3 * mux/driver.h - definitions for the multiplexer driver interface
13 #include <dt-bindings/mux/mux.h>
22 * struct mux_control_ops - Mux controller operations for a mux chip.
23 * @set: Set the state of the given mux controller.
26 int (*set)(struct mux_control *mux, int state);
30 * struct mux_control - Represents a mux controller.
31 * @lock: Protects the mux controller state.
32 * @chip: The mux chip that is handling this mux controller.
33 * @cached_state: The current mux controller state, or -1 if none.
34 * @states: The number of mux controller states.
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| /linux-6.12.1/drivers/clk/ |
| D | clk-mux.c | 27 static inline u32 clk_mux_readl(struct clk_mux *mux) in clk_mux_readl() argument
29 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl()
30 return ioread32be(mux->reg); in clk_mux_readl()
32 return readl(mux->reg); in clk_mux_readl()
35 static inline void clk_mux_writel(struct clk_mux *mux, u32 val) in clk_mux_writel() argument
37 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_writel()
38 iowrite32be(val, mux->reg); in clk_mux_writel()
40 writel(val, mux->reg); in clk_mux_writel()
90 struct clk_mux *mux = to_clk_mux(hw); in clk_mux_get_parent() local
93 val = clk_mux_readl(mux) >> mux->shift; in clk_mux_get_parent()
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| /linux-6.12.1/arch/arm/boot/dts/nuvoton/ |
| D | nuvoton-wpcm450.dtsi | 172 smb3_pins: mux-smb3 {
177 smb4_pins: mux-smb4 {
182 smb5_pins: mux-smb5 {
187 scs1_pins: mux-scs1 {
192 scs2_pins: mux-scs2 {
197 scs3_pins: mux-scs3 {
202 smb0_pins: mux-smb0 {
207 smb1_pins: mux-smb1 {
212 smb2_pins: mux-smb2 {
217 bsp_pins: mux-bsp {
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | mdio-mux-multiplexer.yaml | 4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
14 of a mux producer device. The mux producer can be of any type like mmio mux
15 producer, gpio mux producer or generic register based mux producer.
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
25 mux-controls:
30 - mux-controls
36 mux: mux-controller { // Mux Producer
37 compatible = "reg-mux";
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| /linux-6.12.1/Documentation/i2c/ |
| D | i2c-topology.rst | 10 1. A mux may be needed on the bus to prevent address collisions.
25 I2C transfers, and all adapters with a parent are part of an "i2c-mux"
28 Depending of the particular mux driver, something happens when there is
29 an I2C transfer on one of its child adapters. The mux driver can
30 obviously operate a mux, but it can also do arbitration with an external
31 bus master or open a gate. The mux driver has two operations for this,
40 mux-locked or parent-locked muxes.
43 Mux-locked muxes
46 Mux-locked muxes does not lock the entire parent adapter during the
48 adapter are locked. Mux-locked muxes are mostly interesting if the
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | tegra186-clock.h | 384 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
386 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
388 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
392 /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
394 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
396 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
398 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
400 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
402 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
404 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
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| /linux-6.12.1/net/kcm/ |
| D | kcmsock.c | 59 struct kcm_mux *mux = psock->mux; in kcm_abort_tx_psock() local
63 spin_lock_bh(&mux->lock); in kcm_abort_tx_psock()
66 spin_unlock_bh(&mux->lock); in kcm_abort_tx_psock()
87 spin_unlock_bh(&mux->lock); in kcm_abort_tx_psock()
93 /* RX mux lock held. */
94 static void kcm_update_rx_mux_stats(struct kcm_mux *mux, in kcm_update_rx_mux_stats() argument
97 STRP_STATS_ADD(mux->stats.rx_bytes, in kcm_update_rx_mux_stats()
100 mux->stats.rx_msgs += in kcm_update_rx_mux_stats()
106 static void kcm_update_tx_mux_stats(struct kcm_mux *mux, in kcm_update_tx_mux_stats() argument
109 KCM_STATS_ADD(mux->stats.tx_bytes, in kcm_update_tx_mux_stats()
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| /linux-6.12.1/drivers/clk/sophgo/ |
| D | clk-cv18xx-ip.c | 386 /* MUX */
396 struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw); in mux_enable() local
398 return cv1800_clk_setbit(&mux->common, &mux->gate); in mux_enable()
403 struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw); in mux_disable() local
405 cv1800_clk_clearbit(&mux->common, &mux->gate); in mux_disable()
410 struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw); in mux_is_enabled() local
412 return cv1800_clk_checkbit(&mux->common, &mux->gate); in mux_is_enabled()
418 struct cv1800_clk_mux *mux = data; in mux_round_rate() local
420 return div_helper_round_rate(&mux->div, &mux->common.hw, parent, in mux_round_rate()
427 struct cv1800_clk_mux *mux = hw_to_cv1800_clk_mux(hw); in mux_determine_rate() local
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | clk-krait.c | 23 static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) in __krait_mux_set_sel() argument
30 regval = krait_get_l2_indirect_reg(mux->offset); in __krait_mux_set_sel()
33 if (mux->disable_sec_src_gating) { in __krait_mux_set_sel()
35 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel()
38 regval &= ~(mux->mask << mux->shift); in __krait_mux_set_sel()
39 regval |= (sel & mux->mask) << mux->shift; in __krait_mux_set_sel()
40 if (mux->lpl) { in __krait_mux_set_sel()
41 regval &= ~(mux->mask << (mux->shift + LPL_SHIFT)); in __krait_mux_set_sel()
42 regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT); in __krait_mux_set_sel()
44 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel()
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