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/linux-6.12.1/drivers/pinctrl/qcom/
DKconfig51 tristate "Qualcomm Technologies Inc LPASS LPI pin controller driver"
59 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
63 tristate "Qualcomm Technologies Inc SC7280 LPASS LPI pin controller driver"
68 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
72 tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller driver"
77 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
81 tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
86 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
90 tristate "Qualcomm Technologies Inc SM8250 LPASS LPI pin controller driver"
95 Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
[all …]
DMakefile37 obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) += pinctrl-sc7280-lpass-lpi.o
46 obj-$(CONFIG_PINCTRL_SM4250_LPASS_LPI) += pinctrl-sm4250-lpass-lpi.o
49 obj-$(CONFIG_PINCTRL_SM6115_LPASS_LPI) += pinctrl-sm6115-lpass-lpi.o
56 obj-$(CONFIG_PINCTRL_SM8250_LPASS_LPI) += pinctrl-sm8250-lpass-lpi.o
58 obj-$(CONFIG_PINCTRL_SM8350_LPASS_LPI) += pinctrl-sm8350-lpass-lpi.o
60 obj-$(CONFIG_PINCTRL_SM8450_LPASS_LPI) += pinctrl-sm8450-lpass-lpi.o
62 obj-$(CONFIG_PINCTRL_SM8550_LPASS_LPI) += pinctrl-sm8550-lpass-lpi.o
64 obj-$(CONFIG_PINCTRL_SM8650_LPASS_LPI) += pinctrl-sm8650-lpass-lpi.o
65 obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o
66 obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
Dpinctrl-sm8250-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
130 .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
139 .name = "qcom-sm8250-lpass-lpi-pinctrl",
147 MODULE_DESCRIPTION("QTI SM8250 LPI GPIO pin control driver");
Dpinctrl-sc7280-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
132 .compatible = "qcom,sc7280-lpass-lpi-pinctrl",
141 .name = "qcom-sc7280-lpass-lpi-pinctrl",
149 MODULE_DESCRIPTION("QTI SC7280 LPI GPIO pin control driver");
Dpinctrl-sm8350-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
132 .compatible = "qcom,sm8350-lpass-lpi-pinctrl",
141 .name = "qcom-sm8350-lpass-lpi-pinctrl",
150 MODULE_DESCRIPTION("QTI SM8350 LPI GPIO pin control driver");
Dpinctrl-sm6115-lpass-lpi.c11 #include "pinctrl-lpass-lpi.h"
139 { .compatible = "qcom,sm6115-lpass-lpi-pinctrl", .data = &sm6115_lpi_data },
146 .name = "qcom-sm6115-lpass-lpi-pinctrl",
154 MODULE_DESCRIPTION("QTI SM6115 LPI GPIO pin control driver");
Dpinctrl-sc8280xp-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
169 .compatible = "qcom,sc8280xp-lpass-lpi-pinctrl",
178 .name = "qcom-sc8280xp-lpass-lpi-pinctrl",
186 MODULE_DESCRIPTION("QTI SC8280XP LPI GPIO pin control driver");
Dpinctrl-sm8450-lpass-lpi.c10 #include "pinctrl-lpass-lpi.h"
198 .compatible = "qcom,sm8450-lpass-lpi-pinctrl",
207 .name = "qcom-sm8450-lpass-lpi-pinctrl",
215 MODULE_DESCRIPTION("QTI SM8450 LPI GPIO pin control driver");
/linux-6.12.1/drivers/acpi/riscv/
Dcpuidle.c25 struct acpi_lpi_state *lpi; in acpi_cpu_init_idle() local
40 lpi = &pr->power.lpi_states[i]; in acpi_cpu_init_idle()
48 if (((lpi->address & RISCV_FFH_LPI_TYPE_MASK) != RISCV_FFH_LPI_TYPE_SBI) || in acpi_cpu_init_idle()
49 (lpi->address & RISCV_FFH_LPI_RSVD_MASK)) { in acpi_cpu_init_idle()
50 pr_warn("Invalid LPI entry method %#llx\n", lpi->address); in acpi_cpu_init_idle()
54 state = lpi->address; in acpi_cpu_init_idle()
69 int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
71 u32 state = lpi->address; in acpi_processor_ffh_lpi_enter()
75 lpi->index, in acpi_processor_ffh_lpi_enter()
79 lpi->index, in acpi_processor_ffh_lpi_enter()
/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dqcom,sm8550-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8550 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.
20 - const: qcom,sm8550-lpass-lpi-pinctrl
22 - const: qcom,x1e80100-lpass-lpi-pinctrl
23 - const: qcom,sm8550-lpass-lpi-pinctrl
27 - description: LPASS LPI TLMM Control and Status registers
28 - description: LPASS LPI MCC registers
55 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
80 - $ref: qcom,lpass-lpi-common.yaml#
[all …]
Dqcom,sm6115-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM6115 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM6115 SoC.
19 const: qcom,sm6115-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers
49 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
71 - $ref: qcom,lpass-lpi-common.yaml#
86 compatible = "qcom,sm6115-lpass-lpi-pinctrl";
Dqcom,sm8350-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8350 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8350 SoC.
19 const: qcom,sm8350-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers
51 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
76 - $ref: qcom,lpass-lpi-common.yaml#
91 compatible = "qcom,sm8350-lpass-lpi-pinctrl";
Dqcom,sm4250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM4250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC.
18 const: qcom,sm4250-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
72 - $ref: qcom,lpass-lpi-common.yaml#
86 compatible = "qcom,sm4250-lpass-lpi-pinctrl";
Dqcom,sc8280xp-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SC8280XP SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC.
18 const: qcom,sc8280xp-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
74 - $ref: qcom,lpass-lpi-common.yaml#
88 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
Dqcom,sm8450-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8450 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC.
18 const: qcom,sm8450-lpass-lpi-pinctrl
22 - description: LPASS LPI TLMM Control and Status registers
23 - description: LPASS LPI MCC registers
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
76 - $ref: qcom,lpass-lpi-common.yaml#
90 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
Dqcom,sm8650-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8650 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC.
19 const: qcom,sm8650-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
50 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
75 - $ref: qcom,lpass-lpi-common.yaml#
90 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
Dqcom,sc7280-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SC7280 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC.
18 const: qcom,sc7280-lpass-lpi-pinctrl
38 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
67 - $ref: qcom,lpass-lpi-common.yaml#
74 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
Dqcom,sm8250-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8250 SoC LPASS LPI TLMM
14 (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC.
18 const: qcom,sm8250-lpass-lpi-pinctrl
48 $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
73 - $ref: qcom,lpass-lpi-common.yaml#
87 compatible = "qcom,sm8250-lpass-lpi-pinctrl";
Dqcom,lpass-lpi-common.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-common.yaml#
7 title: Qualcomm SoC LPASS LPI TLMM Common Properties
16 Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm SoCs.
/linux-6.12.1/drivers/acpi/arm64/
Dcpuidle.c20 struct acpi_lpi_state *lpi; in psci_acpi_cpu_init_idle() local
40 lpi = &pr->power.lpi_states[i + 1]; in psci_acpi_cpu_init_idle()
45 state = lpi->address; in psci_acpi_cpu_init_idle()
60 __cpuidle int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
62 u32 state = lpi->address; in acpi_processor_ffh_lpi_enter()
64 if (ARM64_LPI_IS_RETENTION_STATE(lpi->arch_flags)) in acpi_processor_ffh_lpi_enter()
66 lpi->index, state); in acpi_processor_ffh_lpi_enter()
69 lpi->index, state); in acpi_processor_ffh_lpi_enter()
/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac1000.h61 * LPI status, timer and control register offset
66 /* LPI control and status defines */
67 #define LPI_CTRL_STATUS_LPITXA 0x00080000 /* Enable LPI TX Automate */
70 #define LPI_CTRL_STATUS_LPIEN 0x00010000 /* LPI Enable */
71 #define LPI_CTRL_STATUS_RLPIST 0x00000200 /* Receive LPI state */
72 #define LPI_CTRL_STATUS_TLPIST 0x00000100 /* Transmit LPI state */
73 #define LPI_CTRL_STATUS_RLPIEX 0x00000008 /* Receive LPI Exit */
74 #define LPI_CTRL_STATUS_RLPIEN 0x00000004 /* Receive LPI Entry */
75 #define LPI_CTRL_STATUS_TLPIEX 0x00000002 /* Transmit LPI Exit */
76 #define LPI_CTRL_STATUS_TLPIEN 0x00000001 /* Transmit LPI Entry */
Ddwmac4.h179 * LPI status, timer and control register offset
186 /* LPI control and status defines */
187 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
188 #define GMAC4_LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable */
189 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
191 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
192 #define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
193 #define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
194 #define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
195 #define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
/linux-6.12.1/drivers/acpi/
Dprocessor_idle.c935 /* LPI States start at index 3 */ in acpi_processor_evaluate_lpi()
1003 * flat_state_cnt - the number of composite LPI states after the process of flattening
1008 * combine_lpi_states - combine local and parent LPI states to form a composite LPI state
1010 * @local: local LPI state
1011 * @parent: parent LPI state
1012 * @result: composite LPI state
1064 pr_warn("Limiting number of LPI states to max (%d)\n", in flatten_lpi_states()
1146 /* flatten all the LPI states in this level of hierarchy */ in acpi_processor_get_lpi_info()
1166 int __weak acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi) in acpi_processor_ffh_lpi_enter() argument
1172 * acpi_idle_lpi_enter - enters an ACPI any LPI state
[all …]
/linux-6.12.1/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_core.c53 /* Reading this register shall clear all the LPI status bits */ in sxgbe_get_lpi_status()
190 /* Enable the LPI mode for transmit path with Tx automate bit set. in sxgbe_set_eee_mode()
192 * to LPI mode after all outstanding and pending packets are in sxgbe_set_eee_mode()
229 /* Program the timers in the LPI timer control register: in sxgbe_set_eee_timer()
232 * the LPI pattern. in sxgbe_set_eee_timer()
234 * after it has stopped transmitting the LPI pattern. in sxgbe_set_eee_timer()
Dsxgbe_common.h118 /* EEE-LPI mode flags*/
124 /* EEE-LPI Interrupt status flag */
127 /* EEE-LPI Default timer values */
131 /* EEE-LPI Control and status definitions */
243 /* EEE-LPI stats */
348 /* EEE-LPI specific operations */
501 /* EEE-LPI specific members */

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