| /linux-6.12.1/arch/riscv/kvm/ |
| D | aia_imsic.c | 12 #include <linux/irqchip/riscv-imsic.h>
33 struct imsic { struct
44 * 1) Hardware: IMSIC VS-file (vsfile_cpu >= 0)
45 * 2) Software: IMSIC SW-file (vsfile_cpu < 0)
48 /* IMSIC VS-file */
55 /* IMSIC SW-file */
426 /* We can only read clear if we have a IMSIC VS-file */ in imsic_vsfile_read()
496 /* We can only access register if we have a IMSIC VS-file */ in imsic_vsfile_rw()
500 /* Check IMSIC register iselect */ in imsic_vsfile_rw()
524 /* We can only zero-out if we have a IMSIC VS-file */ in imsic_vsfile_local_clear()
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| D | aia_device.c | 11 #include <linux/irqchip/riscv-imsic.h>
98 * VS-level IMSIC pages). in aia_config()
286 /* IMSIC base is required */ in aia_init()
300 /* Update HART index of the IMSIC based on IMSIC base */ in aia_init()
304 /* Initialize IMSIC for this VCPU */ in aia_init()
522 /* Update the IMSIC HW state before entering guest mode */ in kvm_riscv_vcpu_aia_update()
540 /* Reset the IMSIC context */ in kvm_riscv_vcpu_aia_reset()
571 /* Cleanup IMSIC context */ in kvm_riscv_vcpu_aia_deinit()
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| D | aia.c | 13 #include <linux/irqchip/riscv-imsic.h>
585 * We release hgctrl->lock before notifying IMSIC in kvm_riscv_aia_disable()
590 /* Notify IMSIC */ in kvm_riscv_aia_disable()
628 * IMSIC guest files and number of bits in HGEIE in kvm_riscv_aia_init()
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-riscv-imsic-state.c | 7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
59 struct imsic_priv *imsic; variable
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
101 * IMSIC EIEx and EIPx registers. These registers in __imsic_eix_update()
112 * The IMSIC EIEx and EIPx registers are indirectly in __imsic_eix_update()
135 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
155 mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu); in __imsic_local_sync()
169 struct imsic_local_priv *lpriv = this_cpu_ptr(imsic->lpriv); in imsic_local_sync_all()
173 bitmap_fill(lpriv->dirty_bitmap, imsic->global.nr_ids + 1); in imsic_local_sync_all()
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| D | irq-riscv-imsic-early.c | 7 #define pr_fmt(fmt) "riscv-imsic: " fmt
15 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-imsic-state.h"
28 struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu); in imsic_ipi_send()
49 /* Create IMSIC IPI multiplexing */ in imsic_ipi_domain_init()
57 /* Announce that IMSIC is providing IPIs */ in imsic_ipi_domain_init()
58 pr_info("%pfwP: providing IPIs using interrupt %d\n", imsic->fwnode, IMSIC_IPI_ID); in imsic_ipi_domain_init()
91 if (unlikely(!imsic->base_domain)) in imsic_handle_irq()
100 err = generic_handle_domain_irq(imsic->base_domain, vec->hwirq); in imsic_handle_irq()
110 /* Mark per-CPU IMSIC state as online */ in imsic_starting_cpu()
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| D | irq-riscv-imsic-platform.c | 7 #define pr_fmt(fmt) "riscv-imsic: " fmt
23 #include "irq-riscv-imsic-state.h"
31 global = &imsic->global; in imsic_cpu_page_phys()
61 local = per_cpu_ptr(imsic->global.local, vec->cpu); in imsic_irq_retrigger()
135 .name = "IMSIC",
317 if (!imsic || !imsic->fwnode) { in imsic_irqdomain_init()
322 if (imsic->base_domain) { in imsic_irqdomain_init()
323 pr_err("%pfwP: irq domain already created\n", imsic->fwnode); in imsic_irqdomain_init()
328 imsic->base_domain = irq_domain_create_tree(imsic->fwnode, in imsic_irqdomain_init()
329 &imsic_base_domain_ops, imsic); in imsic_irqdomain_init()
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| D | irq-riscv-aplic-msi.c | 13 #include <linux/irqchip/riscv-imsic.h>
197 * controller to be RISC-V AIA IMSIC controller. in aplic_msi_setup()
201 dev_err(dev, "IMSIC global config not found\n"); in aplic_msi_setup()
208 dev_err(dev, "IMSIC guest index bits big for APLIC LHXS\n"); in aplic_msi_setup()
215 dev_err(dev, "IMSIC hart index bits big for APLIC LHXW\n"); in aplic_msi_setup()
222 dev_err(dev, "IMSIC group index bits big for APLIC HHXW\n"); in aplic_msi_setup()
229 dev_err(dev, "IMSIC group index shift should be >= %d\n", in aplic_msi_setup()
235 dev_err(dev, "IMSIC group index shift big for APLIC HHXS\n"); in aplic_msi_setup()
258 * IMSIC and the IMSIC MSI domains are created later through in aplic_msi_setup()
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| D | irq-riscv-imsic-state.h | 10 #include <linux/irqchip/riscv-imsic.h>
63 extern struct imsic_priv *imsic;
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| D | Makefile | 101 obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platf…
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| D | irq-riscv-intc.c | 98 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement in riscv_intc_irq_eoi()
231 * interrupt controllers (such as PLIC, IMSIC and APLIC in riscv_intc_init()
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| D | irq-riscv-aplic-main.c | 10 #include <linux/irqchip/riscv-imsic.h>
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,imsics.yaml | 7 title: RISC-V Incoming MSI Controller (IMSIC)
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
19 a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
20 space to receive MSIs from devices. Each IMSIC interrupt file supports a
24 The device tree of a RISC-V platform will have one IMSIC device tree node
26 IMSIC interrupt files at that privilege level across CPUs (or HARTs).
28 The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
29 follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
30 group is a set of IMSIC interrupt files co-located in MMIO space and we can
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| D | riscv,aplic.yaml | 52 message signaled interrupt controller (IMSIC). If both "msi-parent" and
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| /linux-6.12.1/arch/riscv/include/asm/ |
| D | kvm_aia.h | 33 /* Number of group bits in IMSIC address */
36 /* Position of group bits in IMSIC address */
39 /* Number of hart bits in IMSIC address */
42 /* Number of guest bits in IMSIC address */
69 /* Guest physical address of IMSIC for this VCPU */
72 /* HART index of IMSIC extacted from guest physical address */
75 /* Internal state of IMSIC for this VCPU */
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| /linux-6.12.1/arch/riscv/include/uapi/asm/ |
| D | kvm.h | 311 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
312 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
313 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
346 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
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| /linux-6.12.1/drivers/acpi/riscv/ |
| D | irq.c | 41 * interrupt controller structures and IMSIC before APLIC. The interrupt
43 * the incremental order like RINTC(24)->IMSIC(25)->APLIC(26)->PLIC(27).
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| /linux-6.12.1/include/linux/irqchip/ |
| D | riscv-imsic.h | 72 /* Per-CPU IMSIC addresses */
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| /linux-6.12.1/include/acpi/ |
| D | actbl2.h | 1366 u64 imsic_addr; /* IMSIC base address */
1367 u32 imsic_size; /* IMSIC size */
1378 /* 25: RISC-V IMSIC */
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| /linux-6.12.1/ |
| D | MAINTAINERS | 19823 F: drivers/irqchip/irq-riscv-imsic-*.c
19824 F: drivers/irqchip/irq-riscv-imsic-*.h
19827 F: include/linux/irqchip/riscv-imsic.h
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