Lines Matching full:imsic

7 title: RISC-V Incoming MSI Controller (IMSIC)
14   MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
17   The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
19   a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
20   space to receive MSIs from devices. Each IMSIC interrupt file supports a
24   The device tree of a RISC-V platform will have one IMSIC device tree node
26   IMSIC interrupt files at that privilege level across CPUs (or HARTs).
28   The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform
29   follows a particular scheme defined by the RISC-V AIA specification. A IMSIC
30   group is a set of IMSIC interrupt files co-located in MMIO space and we can
31   have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a
32   RISC-V platform. The MSI target address of a IMSIC interrupt file at given
57       Base address of each IMSIC group.
74       device tree node describes the IMSIC interrupt files. Each node pointed
83       Number of interrupt identities supported by IMSIC interrupt file.
90       Number of interrupt identities are supported by IMSIC guest interrupt
137     // Example 1 (Machine-level IMSIC files with just one group):
154     // Example 2 (Supervisor-level IMSIC files with two groups):