| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | radeon_gart.c | 39 * GART
40 * The GART (Graphics Aperture Remapping Table) is an aperture
46 * Radeon GPUs support both an internal GART, as described above,
47 * and AGP. AGP works similarly, but the GART table is configured
52 * Both AGP and internal GART can be used at the same time, however
55 * This file handles the common internal GART management.
59 * Common GART table functions.
62 * radeon_gart_table_ram_alloc - allocate system ram for gart page table
66 * Allocate system memory for GART page table
68 * gart table to be in system memory.
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| D | rs400.c | 45 /* Check gart size */ in rs400_gart_adjust_size()
56 DRM_ERROR("Unable to use IGP GART size %uM\n", in rs400_gart_adjust_size()
58 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); in rs400_gart_adjust_size()
59 DRM_ERROR("Forcing to 32M GART size\n"); in rs400_gart_adjust_size()
85 if (rdev->gart.ptr) { in rs400_gart_init()
86 WARN(1, "RS400 GART already initialized\n"); in rs400_gart_init()
89 /* Check gart size */ in rs400_gart_init()
102 /* Initialize common gart structure */ in rs400_gart_init()
107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
119 /* Check gart size */ in rs400_gart_enable()
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| D | radeon_drv.h | 62 * 1.6 - Add static GART memory manager
66 * Add GART offset query for getparam
95 * 1.19- Add support for gart table in FB memory and PCIE r300
103 * 1.26- Add support for variable size PCI(E) gart aperture
104 * 1.27- Add support for IGP GART
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| D | rs600.c | 34 * R4XX family. The GART is different from the RS400 one and is very
36 * of the RS600 GART block).
525 * GART.
549 if (rdev->gart.robj) { in rs600_gart_init()
550 WARN(1, "RS600 GART already initialized\n"); in rs600_gart_init()
553 /* Initialize common gart structure */ in rs600_gart_init()
558 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
567 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
568 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
604 rdev->gart.table_addr); in rs600_gart_enable()
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| D | radeon_asic.c | 151 * Removes AGP flags and changes the gart callbacks on AGP
152 * cards when using the internal gart rather than AGP (all asics).
166 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in radeon_agp_disable()
167 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in radeon_agp_disable()
168 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in radeon_agp_disable()
172 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in radeon_agp_disable()
173 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in radeon_agp_disable()
174 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in radeon_agp_disable()
208 .gart = {
276 .gart = {
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| D | r300.c | 83 * rv370,rv380 PCIE GART
122 void __iomem *ptr = rdev->gart.ptr; in rv370_pcie_gart_set_page()
134 if (rdev->gart.robj) { in rv370_pcie_gart_init()
135 WARN(1, "RV370 PCIE GART already initialized\n"); in rv370_pcie_gart_init()
138 /* Initialize common gart structure */ in rv370_pcie_gart_init()
144 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rv370_pcie_gart_init()
145 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in rv370_pcie_gart_init()
146 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in rv370_pcie_gart_init()
147 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in rv370_pcie_gart_init()
157 if (rdev->gart.robj == NULL) { in rv370_pcie_gart_enable()
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_gart.c | 42 * GART
43 * The GART (Graphics Aperture Remapping Table) is an aperture
49 * Radeon GPUs support both an internal GART, as described above,
50 * and AGP. AGP works similarly, but the GART table is configured
55 * Both AGP and internal GART can be used at the same time, however
58 * This file handles the common internal GART management.
62 * Common GART table functions.
71 * This dummy page is used by the driver as a filler for gart entries
72 * when pages are taken out of the GART
108 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
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| D | gmc_v12_0.c | 192 * GART
205 /* Use register 17 for GART */ in gmc_v12_0_flush_vm_hub()
281 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback
669 * vram and gart within the GPU's physical address space.
701 /* set the gart size */ in gmc_v12_0_mc_init()
716 if (adev->gart.bo) { in gmc_v12_0_gart_init()
717 WARN(1, "PCIE GART already initialized\n"); in gmc_v12_0_gart_init()
721 /* Initialize common gart structure */ in gmc_v12_0_gart_init()
726 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v12_0_gart_init()
727 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) | in gmc_v12_0_gart_init()
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| D | amdgpu_gmc.c | 163 * The following is for PTE only. GART does not have PDEs. in amdgpu_gmc_set_pte_pde()
232 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
237 * This function is only used if use GART for FB translation. In such
239 * and gart (aka system memory) access.
246 * address 0. So vram start at address 0 and gart is right after vram.
261 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", in amdgpu_gmc_sysvm_location()
266 * amdgpu_gmc_gart_location - try to find GART location
270 * @gart_placement: GART placement policy with respect to VRAM
272 * Function will place try to place GART before or after VRAM.
273 * If GART size is bigger than space left then we ajust GART size.
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| D | gmc_v11_0.c | 199 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
214 /* Use register 17 for GART */ in gmc_v11_0_flush_gpu_tlb()
669 * vram and gart within the GPU's physical address space.
700 /* set the gart size */ in gmc_v11_0_mc_init()
715 if (adev->gart.bo) { in gmc_v11_0_gart_init()
716 WARN(1, "PCIE GART already initialized\n"); in gmc_v11_0_gart_init()
720 /* Initialize common gart structure */ in gmc_v11_0_gart_init()
725 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v11_0_gart_init()
726 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | in gmc_v11_0_gart_init()
845 * Tears down the driver GART/VM setup (CIK).
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| D | gmc_v10_0.c | 234 * GART
241 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
256 /* Use register 17 for GART */ in gmc_v10_0_flush_gpu_tlb()
700 * vram and gart within the GPU's physical address space.
729 /* set the gart size */ in gmc_v10_0_mc_init()
755 if (adev->gart.bo) { in gmc_v10_0_gart_init()
756 WARN(1, "NAVI10 PCIE GART already initialized\n"); in gmc_v10_0_gart_init()
760 /* Initialize common gart structure */ in gmc_v10_0_gart_init()
765 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v10_0_gart_init()
766 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | in gmc_v10_0_gart_init()
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| D | amdgpu_gmc.h | 220 * gart/vram_start/end field as the later is from
242 /* GART aperture start and end in MC address space
244 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
246 * Under VMID0, logical address inside GART aperture will
247 * be translated through gpuvm gart page table to access
258 * If driver uses GART table for VMID0 FB access, driver finds a hole in
260 * which the first part is vram and the second part is gart (covering
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| D | gmc_v7_0.c | 249 * Set the location of vram, gart, and AGP in the GPU's
310 * vram and gart within the GPU's physical address space (CIK).
385 /* set the gart size */ in gmc_v7_0_mc_init()
443 * GART
450 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
589 * gmc_v7_0_gart_enable - gart enable
605 if (adev->gart.bo == NULL) { in gmc_v7_0_gart_enable()
606 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v7_0_gart_enable()
610 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in gmc_v7_0_gart_enable()
695 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v7_0_gart_enable()
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| D | gmc_v8_0.c | 424 * Set the location of vram, gart, and AGP in the GPU's
496 * vram and gart within the GPU's physical address space (VI).
576 /* set the gart size */ in gmc_v8_0_mc_init()
634 * GART
641 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
804 * gmc_v8_0_gart_enable - gart enable
820 if (adev->gart.bo == NULL) { in gmc_v8_0_gart_enable()
821 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v8_0_gart_enable()
825 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in gmc_v8_0_gart_enable()
927 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v8_0_gart_enable()
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| D | gfxhub_v1_0.c | 61 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v1_0_init_gart_aperture_regs()
65 /* If use GART for FB translation, vmid0 page table covers both in gfxhub_v1_0_init_gart_aperture_regs()
66 * vram and system memory (gart) in gfxhub_v1_0_init_gart_aperture_regs()
141 /* In the case squeezing vram into GART aperture, we don't use in gfxhub_v1_0_init_system_aperture_regs()
325 /* GART Enable. */ in gfxhub_v1_0_gart_enable()
371 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
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| D | amdgpu_gart.h | 30 * GART structures, functions & helpers
44 /* CPU kmapped address of gart table */
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| D | gmc_v6_0.c | 318 /* set the gart size */ in gmc_v6_0_mc_init()
463 if (adev->gart.bo == NULL) { in gmc_v6_0_gart_enable()
464 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v6_0_gart_enable()
469 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in gmc_v6_0_gart_enable()
544 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v6_0_gart_enable()
554 if (adev->gart.bo) { in gmc_v6_0_gart_init()
555 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); in gmc_v6_0_gart_init()
561 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v6_0_gart_init()
562 adev->gart.gart_pte_flags = 0; in gmc_v6_0_gart_init()
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| /linux-6.12.1/arch/x86/kernel/ |
| D | aperture_64.c | 29 #include <asm/gart.h>
39 * the gart aperture that is used.
42 * ==> kexec (with kdump trigger path or gart still enabled)
43 * ==> kernel_small (gart area become e820_reserved)
44 * ==> kexec (with kdump trigger path or gart still enabled)
46 * So don't use 512M below as gart iommu, leave the space for kernel
183 /* old_order could be the value from NB gart setting */ in read_agp()
283 * With kexec/kdump, if the first kernel doesn't shut down the GART and the
284 * second kernel allocates a different GART region, there might be two
285 * overlapping GART regions present:
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| D | amd_gart_64.c | 5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
39 #include <asm/gart.h>
45 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
53 * of only flushing when an mapping is reused. With it true the GART is
79 /* GART can only remap to physical addresses < 1TB */
87 static bool need_flush; /* global flush state. set for each gart wrap */
257 * This driver will not always use a GART mapping, but might have in gart_unmap_page()
551 /* Flush the GART-TLB to remove stale entries */ in enable_gart_translations()
580 pr_info("PCI-DMA: Restoring GART aperture settings\n"); in gart_fixup_northbridges()
596 pr_info("PCI-DMA: Resuming GART IOMMU\n"); in gart_resume()
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| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra20-mc.yaml | 21 Tegra20 Memory Controller includes the GART (Graphics Address Relocation
27 const: nvidia,tegra20-mc-gart
32 - description: GART registers
68 compatible = "nvidia,tegra20-mc-gart";
70 <0x58000000 0x02000000>; /* GART aperture */
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| /linux-6.12.1/arch/x86/include/asm/ |
| D | gart.h | 23 /* GART cache control register bits. */
27 /* K8 On-cpu GART registers */
66 * Don't enable translation but enable GART IO and CPU accesses. in gart_set_size_and_enable()
67 * Also, set DISTLBWALKPRB since GART tables memory is UC. in gart_set_size_and_enable()
84 /* Enable GART translation for this hammer. */ in enable_gart_translation()
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| /linux-6.12.1/arch/powerpc/include/asm/ |
| D | uninorth.h | 53 * GART_BASE register appear to contain the physical address of the GART
55 * GART size in the low order bits (number of GART pages)
57 * The GART format itself is one 32bits word per physical memory page.
62 * Obviously, the GART is not cache coherent and so any change to it
63 * must be flushed to memory (or maybe just make the GART space non
66 * In order to invalidate the GART (which is probably necessary to inval
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| /linux-6.12.1/Documentation/gpu/amdgpu/ |
| D | amdgpu-glossary.rst | 33 GART
37 them. The name GART harkens back to the days of AGP when the platform
58 use by the GPU. These addresses can be mapped into the "GART" GPUVM page
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| /linux-6.12.1/drivers/gpu/drm/nouveau/ |
| D | nouveau_chan.h | 26 struct nvif_object gart; member
64 u32 vram, u32 gart, struct nouveau_channel **);
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| /linux-6.12.1/drivers/char/agp/ |
| D | Kconfig | 14 If you need more texture memory than you can get with the AGP GART
60 tristate "AMD Opteron/Athlon64 on-CPU GART support"
116 This option gives you AGP GART support for the HP Quicksilver
|