5  * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
39 #include <asm/gart.h>
45 static unsigned long iommu_bus_base;	/* GART remapping area (physical) */
53  * of only flushing when an mapping is reused. With it true the GART is
79 /* GART can only remap to physical addresses < 1TB */
87 static bool need_flush;		/* global flush state. set for each gart wrap */
257 	 * This driver will not always use a GART mapping, but might have  in gart_unmap_page()
551 	/* Flush the GART-TLB to remove stale entries */  in enable_gart_translations()
580 	pr_info("PCI-DMA: Restoring GART aperture settings\n");  in gart_fixup_northbridges()
596 	pr_info("PCI-DMA: Resuming GART IOMMU\n");  in gart_resume()
649 		panic("Could not set GART PTEs to uncacheable pages");  in init_amd_gatt()
733 			pr_warn("More than 4GB of memory but GART IOMMU not available.\n");  in gart_iommu_init()
749 	pr_info("PCI-DMA: using GART IOMMU.\n");  in gart_iommu_init()
767 	 * Unmap the IOMMU part of the GART. The alias of the page is  in gart_iommu_init()
769 	 * coherency across the GART remapping. The unmapping avoids  in gart_iommu_init()
772 	 * the backing memory. The GART address is only used by PCI  in gart_iommu_init()
778 	 * Tricky. The GART table remaps the physical memory range,  in gart_iommu_init()
789 	 * GART hardware.  Doing it early leaves the possibility  in gart_iommu_init()
790 	 * of stale cache entries that can lead to GART PTE  in gart_iommu_init()