| /linux-6.12.1/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 6 #include <dt-bindings/clock/sifive-fu540-prci.h>
11 compatible = "sifive,fu540-c000", "sifive,fu540";
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
196 compatible = "sifive,fu540-c000-prci";
202 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
210 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
219 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
227 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
239 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
250 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
[all …]
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| D | hifive-unleashed-a00.dts | 4 #include "fu540-c000.dtsi"
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
15 "sifive,fu540";
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| D | fu740-c000.dtsi | 185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
276 compatible = "sifive,fu540-c000-gem";
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/sifive/ |
| D | fu540-prci.yaml | 5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
14 On the FU540 family of SoCs, most system-wide clock and reset integration
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
26 const: sifive,fu540-c000-prci
55 compatible = "sifive,fu540-c000-prci";
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| /linux-6.12.1/Documentation/devicetree/bindings/dma/ |
| D | sifive,fu540-c000-pdma.yaml | 4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 - sifive,fu540-c000-pdma
38 "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the
39 SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block
68 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
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| /linux-6.12.1/Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 30 - sifive,fu540-c000-pwm
35 compatible strings are "sifive,fu540-c000-pwm" and
37 SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
53 Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator.
66 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
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| /linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
| D | sifive,gpio.yaml | 16 - sifive,fu540-c000-gpio
69 - sifive,fu540-c000-gpio
79 #include <dt-bindings/clock/sifive-fu540-prci.h>
81 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
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| /linux-6.12.1/drivers/clk/sifive/ |
| D | fu540-prci.h | 8 * The FU540 PRCI implements clock and reset control for the SiFive
9 * FU540-C000 chip. This driver assumes that it has sole control
16 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
25 #include <dt-bindings/clock/sifive-fu540-prci.h>
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| D | Kconfig | 20 FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
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| D | sifive-prci.c | 12 #include "fu540-prci.h"
602 {.compatible = "sifive,fu540-c000-prci", .data = &prci_clk_fu540},
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| /linux-6.12.1/Documentation/devicetree/bindings/spi/ |
| D | spi-sifive.yaml | 21 - sifive,fu540-c000-spi
28 "sifive,fu540-c000-spi" and "sifive,fu740-c000-spi" for the SiFive SPI v0
29 as integrated onto the SiFive FU540 and FU740 chip resp, and "sifive,spi0"
76 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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| /linux-6.12.1/Documentation/devicetree/bindings/cache/ |
| D | sifive,ccache0.yaml | 25 - sifive,fu540-c000-ccache
37 - sifive,fu540-c000-ccache
48 - const: sifive,fu540-c000-ccache
161 compatible = "sifive,fu540-c000-ccache", "cache";
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| /linux-6.12.1/Documentation/devicetree/bindings/serial/ |
| D | sifive-serial.yaml | 21 - sifive,fu540-c000-uart
56 #include <dt-bindings/clock/sifive-fu540-prci.h>
58 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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| /linux-6.12.1/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 33 - sifive,fu540-c000-clint # SiFive FU540
74 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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| /linux-6.12.1/drivers/dma/sf-pdma/ |
| D | sf-pdma.h | 3 * SiFive FU540 Platform DMA driver
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
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| D | sf-pdma.c | 3 * SiFive FU540 Platform DMA driver
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
623 .compatible = "sifive,fu540-c000-pdma",
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| /linux-6.12.1/Documentation/devicetree/bindings/riscv/ |
| D | sifive.yaml | 24 - const: sifive,fu540-c000
25 - const: sifive,fu540
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | cdns,macb.yaml | 57 - sifive,fu540-c000-gem # SiFive FU540-C000 SoC
71 - description: GEMGXL Management block registers on SiFive FU540-C000 SoC
171 const: sifive,fu540-c000-gem
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| /linux-6.12.1/Documentation/devicetree/bindings/sifive/ |
| D | sifive-blocks-ip-versioning.txt | 30 "sifive,fu540-c000-uart". This way, if SoC-specific
38 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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| /linux-6.12.1/Documentation/devicetree/bindings/i2c/ |
| D | opencores,i2c-ocores.yaml | 22 - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 61 - sifive,fu540-c000-plic
166 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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| /linux-6.12.1/arch/riscv/boot/dts/microchip/ |
| D | mpfs.dtsi | 210 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
222 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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| /linux-6.12.1/drivers/clk/analogbits/ |
| D | wrpll-cln28hpc.c | 20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
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| /linux-6.12.1/drivers/i2c/busses/ |
| D | i2c-ocores.c | 86 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
469 .compatible = "sifive,fu540-c000-i2c",
679 "sifive,fu540-c000-i2c")) { in ocores_i2c_probe()
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| /linux-6.12.1/drivers/cache/ |
| D | sifive_ccache.c | 121 { .compatible = "sifive,fu540-c000-ccache" },
|