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/linux-6.12.1/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
15 "sifive,fu540";
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
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Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dsifive,fu540-c000-pdma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
26 - $ref: dma-controller.yaml#
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/linux-6.12.1/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Walmsley <paul.walmsley@sifive.com>
19 numbers can be found here -
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
24 - $ref: pwm.yaml#
29 - enum:
30 - sifive,fu540-c000-pwm
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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Walmsley <paul.walmsley@sifive.com>
15 - enum:
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
18 - canaan,k210-gpiohs
19 - const: sifive,gpio0
30 interrupt-controller: true
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/linux-6.12.1/Documentation/devicetree/bindings/cache/
Dsifive,ccache0.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 acts as directory-based coherency manager.
24 - sifive,ccache0
25 - sifive,fu540-c000-ccache
26 - sifive,fu740-c000-ccache
29 - compatible
34 - items:
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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dspi-sifive.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: spi-controller.yaml#
20 - enum:
21 - sifive,fu540-c000-spi
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/linux-6.12.1/Documentation/devicetree/bindings/clock/sifive/
Dfu540-prci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 On the FU540 family of SoCs, most system-wide clock and reset integration
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
26 const: sifive,fu540-c000-prci
33 - description: high frequency clock.
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/linux-6.12.1/Documentation/devicetree/bindings/serial/
Dsifive-serial.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: serial.yaml#
20 - enum:
21 - sifive,fu540-c000-uart
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/linux-6.12.1/drivers/clk/sifive/
Dfu540-prci.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018-2021 SiFive, Inc.
4 * Copyright (C) 2018-2019 Wesley Terpstra
5 * Copyright (C) 2018-2019 Paul Walmsley
6 * Copyright (C) 2020-2021 Zong Li
8 * The FU540 PRCI implements clock and reset control for the SiFive
9 * FU540-C000 chip. This driver assumes that it has sole control
13 * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
16 * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
25 #include <dt-bindings/clock/sifive-fu540-prci.h>
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Dsifive-prci.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "sifive-prci.h"
12 #include "fu540-prci.h"
13 #include "fu740-prci.h"
20 * __prci_readl() - read from a PRCI register
34 return readl_relaxed(pd->va + offs); in __prci_readl()
39 writel_relaxed(v, pd->va + offs); in __prci_writel()
42 /* WRPLL-related private functions */
45 * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
64 c->divr = v; in __prci_wrpll_unpack()
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/linux-6.12.1/Documentation/devicetree/bindings/riscv/
Dsifive.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
21 - items:
22 - enum:
23 - sifive,hifive-unleashed-a00
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dcdns,macb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Claudiu Beznea <claudiu.beznea@microchip.com>
16 - items:
17 - enum:
18 - cdns,at91rm9200-emac # Atmel at91rm9200 SoC
19 - const: cdns,emac # Generic
21 - items:
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/linux-6.12.1/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
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/linux-6.12.1/drivers/dma/sf-pdma/
Dsf-pdma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SiFive FU540 Platform DMA driver
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
20 #include <linux/dma-direction.h>
23 #include "../virt-dma.h"
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Dsf-pdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SiFive FU540 Platform DMA driver
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
21 #include <linux/dma-mapping.h>
26 #include "sf-pdma.h"
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/linux-6.12.1/Documentation/devicetree/bindings/sifive/
Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
9 IP block-specific DT compatible strings are contained within the HDL,
10 in the form "sifive,<ip-block-name><integer version number>".
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
17 auto-discovery, the maintainers of these IP blocks intend to increment
25 upstream sifive-blocks commits. It is expected that most drivers will
26 match on these IP block-specific compatible strings.
29 continue to specify an SoC-specific compatible string value, such as
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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/linux-6.12.1/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux-6.12.1/drivers/clk/analogbits/
Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
33 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
41 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
44 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */
73 * __wrpll_calc_filter_range() - determine PLL loop filter bandwidth
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/linux-6.12.1/drivers/i2c/busses/
Di2c-ocores.c1 // SPDX-License-Identifier: GPL-2.0
3 * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
22 #include <linux/platform_data/i2c-ocores.h>
86 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
90 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_8()
95 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16()
100 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32()
105 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16be()
110 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32be()
115 return ioread8(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_8()
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/linux-6.12.1/drivers/cache/
Dsifive_ccache.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2022 SiFive, Inc.
22 #include <asm/dma-noncoherent.h>
82 return -EINVAL; in ccache_write()
86 return -EINVAL; in ccache_write()
121 { .compatible = "sifive,fu540-c000-ccache" },
122 { .compatible = "sifive,fu740-c000-ccache" },
123 { .compatible = "starfive,jh7100-ccache",
198 if (this_leaf->level == level) in ccache_get_priv_group()
254 struct device *dev = &pdev->dev; in sifive_ccache_probe()
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/linux-6.12.1/drivers/gpio/
Dgpio-sifive.c1 // SPDX-License-Identifier: GPL-2.0
47 raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags); in sifive_gpio_set_ie()
48 trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0; in sifive_gpio_set_ie()
49 regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset), in sifive_gpio_set_ie()
51 regmap_update_bits(chip->regs, SIFIVE_GPIO_FALL_IE, BIT(offset), in sifive_gpio_set_ie()
53 regmap_update_bits(chip->regs, SIFIVE_GPIO_HIGH_IE, BIT(offset), in sifive_gpio_set_ie()
55 regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset), in sifive_gpio_set_ie()
57 raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags); in sifive_gpio_set_ie()
66 if (offset < 0 || offset >= gc->ngpio) in sifive_gpio_irq_set_type()
67 return -EINVAL; in sifive_gpio_irq_set_type()
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