/linux-6.12.1/drivers/memory/tegra/ |
D | tegra20-emc.c | 216 * There are multiple sources in the EMC driver which could request 237 struct tegra_emc *emc = data; in tegra_emc_isr() local 241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr() 247 dev_err_ratelimited(emc->dev, in tegra_emc_isr() 251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr() 256 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument 262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing() 263 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing() 264 timing = &emc->timings[i]; in tegra_emc_find_timing() 270 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing() [all …]
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D | tegra30-emc.c | 5 * Based on downstream driver from NVIDIA and tegra124-emc.c 387 * There are multiple sources in the EMC driver which could request 398 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument 403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing() 405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing() 409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing() 418 struct tegra_emc *emc = data; in tegra_emc_isr() local 422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr() 428 dev_err_ratelimited(emc->dev, in tegra_emc_isr() 432 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr() [all …]
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D | tegra210-emc-core.c | 21 #include "tegra210-emc.h" 69 next->trim_perch_regs[EMC ## chan ## \ 561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local 564 if (!emc->last) in tegra210_emc_train() 567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train() 569 if (emc->sequence->periodic_compensation) in tegra210_emc_train() 570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train() 572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train() 574 mod_timer(&emc->training, in tegra210_emc_train() 575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train() [all …]
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D | tegra186-emc.c | 42 * to control the EMC frequency. The top-level directory can be found here: 44 * /sys/kernel/debug/emc 49 * EMC frequencies. 53 * configured EMC frequency, this will cause the frequency to be 58 * the value is lower than the currently configured EMC frequency, this 63 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, in tegra186_emc_validate_rate() argument 68 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate() 69 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate() 78 struct tegra186_emc *emc = s->private; in tegra186_emc_debug_available_rates_show() local 82 for (i = 0; i < emc->num_dvfs; i++) { in tegra186_emc_debug_available_rates_show() [all …]
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D | tegra124-emc.c | 507 * There are multiple sources in the EMC driver which could request 518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument 521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel() 522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel() 525 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument 530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing() 533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing() 539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing() 542 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument 547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal() [all …]
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D | tegra210-emc-cc-r21021.c | 14 #include "tegra210-emc.h" 36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument 108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%u) EMA: %u\n", \ 133 static void tegra210_emc_get_clktree_delay(struct tegra210_emc *emc, in tegra210_emc_get_clktree_delay() argument 136 struct tegra210_emc_timing *curr = emc->last; in tegra210_emc_get_clktree_delay() 145 tegra210_emc_start_periodic_compensation(emc); in tegra210_emc_get_clktree_delay() 148 for (d = 0; d < emc->num_devices; d++) { in tegra210_emc_get_clktree_delay() 150 msb = tegra210_emc_mrr_read(emc, 2 - d, 19); in tegra210_emc_get_clktree_delay() 151 lsb = tegra210_emc_mrr_read(emc, 2 - d, 18); in tegra210_emc_get_clktree_delay() 153 for (c = 0; c < emc->num_channels; c++) { in tegra210_emc_get_clktree_delay() [all …]
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D | tegra210-emc-table.c | 8 #include "tegra210-emc.h" 15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local 21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init() 33 if (emc->derated) { in tegra210_emc_table_device_init() 34 dev_warn(dev, "excess EMC table '%s'\n", rmem->name); in tegra210_emc_table_device_init() 38 if (emc->nominal) { in tegra210_emc_table_device_init() 39 if (count != emc->num_timings) { in tegra210_emc_table_device_init() 41 count, emc->num_timings); in tegra210_emc_table_device_init() 46 emc->derated = timings; in tegra210_emc_table_device_init() 48 emc->num_timings = count; in tegra210_emc_table_device_init() [all …]
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D | Makefile | 16 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o 17 obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o 18 obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o 19 obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o 20 obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o 21 obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o 22 obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o 23 obj-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186-emc.o 25 tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
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/linux-6.12.1/arch/arm/boot/dts/nvidia/ |
D | tegra124-apalis-emc.dtsi | 11 emc-timings-1 { 18 clock-names = "emc-parent"; 25 clock-names = "emc-parent"; 32 clock-names = "emc-parent"; 39 clock-names = "emc-parent"; 46 clock-names = "emc-parent"; 53 clock-names = "emc-parent"; 60 clock-names = "emc-parent"; 67 clock-names = "emc-parent"; 74 clock-names = "emc-parent"; [all …]
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D | tegra124-jetson-tk1-emc.dtsi | 7 emc-timings-3 { 14 clock-names = "emc-parent"; 21 clock-names = "emc-parent"; 28 clock-names = "emc-parent"; 35 clock-names = "emc-parent"; 42 clock-names = "emc-parent"; 49 clock-names = "emc-parent"; 56 clock-names = "emc-parent"; 63 clock-names = "emc-parent"; 70 clock-names = "emc-parent"; [all …]
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D | tegra124-nyan-blaze-emc.dtsi | 7 emc-timings-1 { 14 clock-names = "emc-parent"; 21 clock-names = "emc-parent"; 28 clock-names = "emc-parent"; 35 clock-names = "emc-parent"; 42 clock-names = "emc-parent"; 49 clock-names = "emc-parent"; 56 clock-names = "emc-parent"; 63 clock-names = "emc-parent"; 72 clock-names = "emc-parent"; [all …]
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D | tegra30-asus-tf300t.dts | 146 emc-timings-0 { 211 emc-timings-1 { 276 emc-timings-2 { 343 emc-timings-0 { 350 nvidia,emc-auto-cal-interval = <0x001fffff>; 351 nvidia,emc-mode-1 = <0x80100003>; 352 nvidia,emc-mode-2 = <0x80200008>; 353 nvidia,emc-mode-reset = <0x80001221>; 354 nvidia,emc-zcal-cnt-long = <0x00000040>; 355 nvidia,emc-cfg-dyn-self-ref; [all …]
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D | tegra30-asus-tf300tg.dts | 220 emc-timings-0 { 285 emc-timings-1 { 350 emc-timings-2 { 417 emc-timings-0 { 424 nvidia,emc-auto-cal-interval = <0x001fffff>; 425 nvidia,emc-mode-1 = <0x80100003>; 426 nvidia,emc-mode-2 = <0x80200048>; 427 nvidia,emc-mode-reset = <0x80001221>; 428 nvidia,emc-zcal-cnt-long = <0x00000040>; 429 nvidia,emc-cfg-dyn-self-ref; [all …]
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D | tegra30-asus-tf700t.dts | 141 emc-timings-0 { 206 emc-timings-1 { 273 emc-timings-0 { 280 nvidia,emc-auto-cal-interval = <0x001fffff>; 281 nvidia,emc-mode-1 = <0x80100003>; 282 nvidia,emc-mode-2 = <0x80200008>; 283 nvidia,emc-mode-reset = <0x80001221>; 284 nvidia,emc-zcal-cnt-long = <0x00000040>; 285 nvidia,emc-cfg-dyn-self-ref; 286 nvidia,emc-cfg-periodic-qrst; [all …]
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D | tegra30-asus-tf201.dts | 112 emc-timings-0 { 167 emc-timings-1 { 224 emc-timings-0 { 231 nvidia,emc-auto-cal-interval = <0x001fffff>; 232 nvidia,emc-mode-1 = <0x00010022>; 233 nvidia,emc-mode-2 = <0x00020001>; 234 nvidia,emc-mode-reset = <0x00000000>; 235 nvidia,emc-zcal-cnt-long = <0x00000009>; 236 nvidia,emc-cfg-periodic-qrst; 238 nvidia,emc-configuration = < 0x00000001 [all …]
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D | tegra124-nyan-big-emc.dtsi | 7 emc-timings-1 { 14 clock-names = "emc-parent"; 21 clock-names = "emc-parent"; 28 clock-names = "emc-parent"; 35 clock-names = "emc-parent"; 42 clock-names = "emc-parent"; 49 clock-names = "emc-parent"; 56 clock-names = "emc-parent"; 63 clock-names = "emc-parent"; 70 clock-names = "emc-parent"; [all …]
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D | tegra30-lg-p880.dts | 120 emc-timings-0 { 197 emc-timings-0 { 204 nvidia,emc-auto-cal-interval = <0x001fffff>; 205 nvidia,emc-mode-1 = <0x00010022>; 206 nvidia,emc-mode-2 = <0x00020001>; 207 nvidia,emc-mode-reset = <0x00000000>; 208 nvidia,emc-zcal-cnt-long = <0x00000009>; 209 nvidia,emc-cfg-dyn-self-ref; 210 nvidia,emc-cfg-periodic-qrst; 212 nvidia,emc-configuration = < 0x00000000 [all …]
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D | tegra30-lg-p895.dts | 116 emc-timings-2 { 193 emc-timings-2 { 200 nvidia,emc-auto-cal-interval = <0x001fffff>; 201 nvidia,emc-mode-1 = <0x00010022>; 202 nvidia,emc-mode-2 = <0x00020001>; 203 nvidia,emc-mode-reset = <0x00000000>; 204 nvidia,emc-zcal-cnt-long = <0x00000009>; 205 nvidia,emc-cfg-periodic-qrst; 207 nvidia,emc-configuration = < 0x00000000 235 nvidia,emc-auto-cal-interval = <0x001fffff>; [all …]
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D | tegra30-pegatron-chagall.dts | 1535 emc-timings-0 { 1590 emc-timings-1 { 1645 emc-timings-2 { 1700 emc-timings-3 { 1757 emc-timings-0 { 1764 nvidia,emc-auto-cal-interval = <0x001fffff>; 1765 nvidia,emc-mode-1 = <0x00010022>; 1766 nvidia,emc-mode-2 = <0x00020001>; 1767 nvidia,emc-mode-reset = <0x00000000>; 1768 nvidia,emc-zcal-cnt-long = <0x00000009>; [all …]
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D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 { 159 emc-timings-1 { 315 emc-timings-0 { 321 nvidia,emc-auto-cal-interval = <0x001fffff>; 322 nvidia,emc-mode-1 = <0x80100003>; 323 nvidia,emc-mode-2 = <0x80200008>; 324 nvidia,emc-mode-reset = <0x80001221>; 325 nvidia,emc-zcal-cnt-long = <0x00000040>; 326 nvidia,emc-cfg-dyn-self-ref; 327 nvidia,emc-cfg-periodic-qrst; [all …]
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/linux-6.12.1/drivers/clk/tegra/ |
D | clk-tegra20-emc.c | 3 * Based on drivers/clk/tegra/clk-emc.c 10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt 57 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_recalc_rate() local 60 val = readl_relaxed(emc->reg); in emc_recalc_rate() 68 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_get_parent() local 70 return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT; in emc_get_parent() 75 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_set_parent() local 78 val = readl_relaxed(emc->reg); in emc_set_parent() 84 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter) in emc_set_parent() 89 if (emc->mc_same_freq) in emc_set_parent() [all …]
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D | clk-tegra210-emc.c | 53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local 57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent() 66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local 74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate() 75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate() 81 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_recalc_rate() 92 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_round_rate() local 93 struct tegra210_clk_emc_provider *provider = emc->provider; in tegra210_clk_emc_round_rate() 107 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, in tegra210_clk_emc_find_parent() argument 110 struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); in tegra210_clk_emc_find_parent() [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
D | nvidia,tegra124-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml# 14 The EMC interfaces with the off-chip SDRAM to service the request stream 19 const: nvidia,tegra124-emc 30 - const: emc 51 "^emc-timings-[0-9]+$": 71 nvidia,emc-auto-cal-config: 77 nvidia,emc-auto-cal-config2: 83 nvidia,emc-auto-cal-config3: 89 nvidia,emc-auto-cal-interval: 96 nvidia,emc-bgbias-ctl0: [all …]
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D | nvidia,tegra30-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml# 15 The EMC interfaces with the off-chip SDRAM to service the request stream 16 sent from Memory Controller. The EMC also has various performance-affecting 18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2, 23 const: nvidia,tegra30-emc 53 "^emc-timings-[0-9]+$": 71 nvidia,emc-auto-cal-interval: 78 nvidia,emc-mode-1: 83 nvidia,emc-mode-2: 88 nvidia,emc-mode-reset: [all …]
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D | nvidia,tegra20-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml# 15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to 16 service the request stream sent from Memory Controller. The EMC also has 18 parameters and initialization settings. Tegra20 EMC supports multiple JEDEC 23 const: nvidia,tegra20-emc 61 If present, the emc-tables@ sub-nodes will be addressed. 64 emc-table: 68 const: nvidia,tegra20-emc-table 82 nvidia,emc-registers: 84 EMC timing characterization data. These are the registers [all …]
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