Lines Matching full:emc
216 * There are multiple sources in the EMC driver which could request
237 struct tegra_emc *emc = data; in tegra_emc_isr() local
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
256 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
263 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
264 timing = &emc->timings[i]; in tegra_emc_find_timing()
270 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
277 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
279 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in emc_prepare_timing_change()
285 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
291 emc->regs + emc_timing_registers[i]); in emc_prepare_timing_change()
294 readl_relaxed(emc->regs + emc_timing_registers[i - 1]); in emc_prepare_timing_change()
299 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) in emc_complete_timing_change() argument
304 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); in emc_complete_timing_change()
309 emc->regs + EMC_TIMING_CONTROL); in emc_complete_timing_change()
313 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
317 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); in emc_complete_timing_change()
327 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); in tegra_emc_clk_change_notify() local
333 err = emc_prepare_timing_change(emc, cnd->new_rate); in tegra_emc_clk_change_notify()
337 err = emc_prepare_timing_change(emc, cnd->old_rate); in tegra_emc_clk_change_notify()
341 err = emc_complete_timing_change(emc, true); in tegra_emc_clk_change_notify()
345 err = emc_complete_timing_change(emc, false); in tegra_emc_clk_change_notify()
355 static int load_one_timing_from_dt(struct tegra_emc *emc, in load_one_timing_from_dt() argument
362 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { in load_one_timing_from_dt()
363 dev_err(emc->dev, "incompatible DT node: %pOF\n", node); in load_one_timing_from_dt()
369 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", in load_one_timing_from_dt()
374 err = of_property_read_u32_array(node, "nvidia,emc-registers", in load_one_timing_from_dt()
378 dev_err(emc->dev, in load_one_timing_from_dt()
379 "timing %pOF: failed to read emc timing data: %d\n", in load_one_timing_from_dt()
385 * The EMC clock rate is twice the bus rate, and the bus rate is in load_one_timing_from_dt()
390 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", in load_one_timing_from_dt()
410 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, in tegra_emc_load_timings_from_dt() argument
419 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); in tegra_emc_load_timings_from_dt()
423 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
425 if (!emc->timings) in tegra_emc_load_timings_from_dt()
428 timing = emc->timings; in tegra_emc_load_timings_from_dt()
434 err = load_one_timing_from_dt(emc, timing++, child); in tegra_emc_load_timings_from_dt()
438 emc->num_timings++; in tegra_emc_load_timings_from_dt()
441 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
444 dev_info_once(emc->dev, in tegra_emc_load_timings_from_dt()
446 emc->num_timings, in tegra_emc_load_timings_from_dt()
448 emc->timings[0].rate / 1000000, in tegra_emc_load_timings_from_dt()
449 emc->timings[emc->num_timings - 1].rate / 1000000); in tegra_emc_load_timings_from_dt()
455 tegra_emc_find_node_by_ram_code(struct tegra_emc *emc) in tegra_emc_find_node_by_ram_code() argument
457 struct device *dev = emc->dev; in tegra_emc_find_node_by_ram_code()
462 if (emc->mrr_error) { in tegra_emc_find_node_by_ram_code()
477 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; in tegra_emc_find_node_by_ram_code()
478 np = of_find_node_by_name(np, "emc-tables")) { in tegra_emc_find_node_by_ram_code()
491 info->manufacturer_id != emc->manufacturer_id) in tegra_emc_find_node_by_ram_code()
495 info->revision_id1 != emc->revision_id1) in tegra_emc_find_node_by_ram_code()
499 info->revision_id2 != emc->revision_id2) in tegra_emc_find_node_by_ram_code()
502 if (info->density != emc->basic_conf4.density) in tegra_emc_find_node_by_ram_code()
505 if (info->io_width != emc->basic_conf4.io_width) in tegra_emc_find_node_by_ram_code()
508 if (info->arch_type != emc->basic_conf4.arch_type) in tegra_emc_find_node_by_ram_code()
535 static int emc_read_lpddr_mode_register(struct tegra_emc *emc, in emc_read_lpddr_mode_register() argument
545 writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS); in emc_read_lpddr_mode_register()
551 writel_relaxed(val, emc->regs + EMC_MRR); in emc_read_lpddr_mode_register()
554 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val, in emc_read_lpddr_mode_register()
558 dev_err(emc->dev, "mode register %u read failed: %d\n", in emc_read_lpddr_mode_register()
560 emc->mrr_error = true; in emc_read_lpddr_mode_register()
565 val = readl_relaxed(emc->regs + EMC_MRR); in emc_read_lpddr_mode_register()
571 static void emc_read_lpddr_sdram_info(struct tegra_emc *emc, in emc_read_lpddr_sdram_info() argument
576 emc_read_lpddr_mode_register(emc, emem_dev, 5, &emc->manufacturer_id); in emc_read_lpddr_sdram_info()
577 emc_read_lpddr_mode_register(emc, emem_dev, 6, &emc->revision_id1); in emc_read_lpddr_sdram_info()
578 emc_read_lpddr_mode_register(emc, emem_dev, 7, &emc->revision_id2); in emc_read_lpddr_sdram_info()
579 emc_read_lpddr_mode_register(emc, emem_dev, 8, &emc->basic_conf4.value); in emc_read_lpddr_sdram_info()
584 …dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u dens… in emc_read_lpddr_sdram_info()
585 emem_dev, emc->manufacturer_id, in emc_read_lpddr_sdram_info()
586 lpddr2_jedec_manufacturer(emc->manufacturer_id), in emc_read_lpddr_sdram_info()
587 emc->revision_id1, emc->revision_id2, in emc_read_lpddr_sdram_info()
588 4 >> emc->basic_conf4.arch_type, in emc_read_lpddr_sdram_info()
589 64 << emc->basic_conf4.density, in emc_read_lpddr_sdram_info()
590 32 >> emc->basic_conf4.io_width); in emc_read_lpddr_sdram_info()
593 static int emc_setup_hw(struct tegra_emc *emc) in emc_setup_hw() argument
602 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
606 * or power-down state on EMC clock change. in emc_setup_hw()
610 dev_err(emc->dev, in emc_setup_hw()
615 /* enable EMC and CAR to handshake on PLL divider/source changes */ in emc_setup_hw()
617 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
620 writel_relaxed(intmask, emc->regs + EMC_INTMASK); in emc_setup_hw()
621 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
624 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
629 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
631 emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
634 emc->dram_bus_width = 16; in emc_setup_hw()
636 emc->dram_bus_width = 32; in emc_setup_hw()
655 emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG_0); in emc_setup_hw()
658 dev_info_once(emc->dev, "%ubit DRAM bus, %u %s %s attached\n", in emc_setup_hw()
659 emc->dram_bus_width, emem_numdev, dram_type_str, in emc_setup_hw()
664 emc_read_lpddr_sdram_info(emc, emem_numdev, in emc_setup_hw()
678 struct tegra_emc *emc = arg; in emc_round_rate() local
681 if (!emc->num_timings) in emc_round_rate()
682 return clk_get_rate(emc->clk); in emc_round_rate()
684 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
686 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
687 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
690 if (emc->timings[i].rate > max_rate) { in emc_round_rate()
693 if (emc->timings[i].rate < min_rate) in emc_round_rate()
697 if (emc->timings[i].rate < min_rate) in emc_round_rate()
700 timing = &emc->timings[i]; in emc_round_rate()
705 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", in emc_round_rate()
713 static void tegra_emc_rate_requests_init(struct tegra_emc *emc) in tegra_emc_rate_requests_init() argument
718 emc->requested_rate[i].min_rate = 0; in tegra_emc_rate_requests_init()
719 emc->requested_rate[i].max_rate = ULONG_MAX; in tegra_emc_rate_requests_init()
723 static int emc_request_rate(struct tegra_emc *emc, in emc_request_rate() argument
728 struct emc_rate_request *req = emc->requested_rate; in emc_request_rate()
745 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", in emc_request_rate()
751 * EMC rate-changes should go via OPP API because it manages voltage in emc_request_rate()
754 err = dev_pm_opp_set_rate(emc->dev, min_rate); in emc_request_rate()
758 emc->requested_rate[type].min_rate = new_min_rate; in emc_request_rate()
759 emc->requested_rate[type].max_rate = new_max_rate; in emc_request_rate()
764 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_min_rate() argument
767 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_min_rate()
770 mutex_lock(&emc->rate_lock); in emc_set_min_rate()
771 ret = emc_request_rate(emc, rate, req->max_rate, type); in emc_set_min_rate()
772 mutex_unlock(&emc->rate_lock); in emc_set_min_rate()
777 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_max_rate() argument
780 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_max_rate()
783 mutex_lock(&emc->rate_lock); in emc_set_max_rate()
784 ret = emc_request_rate(emc, req->min_rate, rate, type); in emc_set_max_rate()
785 mutex_unlock(&emc->rate_lock); in emc_set_max_rate()
794 * to control the EMC frequency. The top-level directory can be found here:
796 * /sys/kernel/debug/emc
801 * EMC frequencies.
805 * configured EMC frequency, this will cause the frequency to be
810 * the value is lower than the currently configured EMC frequency, this
815 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
819 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
820 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
828 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show() local
832 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
833 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
845 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_get() local
847 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
854 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_set() local
857 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
860 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_min_rate_set()
864 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
875 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_get() local
877 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
884 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_set() local
887 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
890 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_max_rate_set()
894 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
903 static void tegra_emc_debugfs_init(struct tegra_emc *emc) in tegra_emc_debugfs_init() argument
905 struct device *dev = emc->dev; in tegra_emc_debugfs_init()
909 emc->debugfs.min_rate = ULONG_MAX; in tegra_emc_debugfs_init()
910 emc->debugfs.max_rate = 0; in tegra_emc_debugfs_init()
912 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
913 if (emc->timings[i].rate < emc->debugfs.min_rate) in tegra_emc_debugfs_init()
914 emc->debugfs.min_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
916 if (emc->timings[i].rate > emc->debugfs.max_rate) in tegra_emc_debugfs_init()
917 emc->debugfs.max_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
920 if (!emc->num_timings) { in tegra_emc_debugfs_init()
921 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra_emc_debugfs_init()
922 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra_emc_debugfs_init()
925 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra_emc_debugfs_init()
926 emc->debugfs.max_rate); in tegra_emc_debugfs_init()
929 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra_emc_debugfs_init()
930 emc->clk); in tegra_emc_debugfs_init()
933 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra_emc_debugfs_init()
935 debugfs_create_file("available_rates", 0444, emc->debugfs.root, in tegra_emc_debugfs_init()
936 emc, &tegra_emc_debug_available_rates_fops); in tegra_emc_debugfs_init()
937 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
938 emc, &tegra_emc_debug_min_rate_fops); in tegra_emc_debugfs_init()
939 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
940 emc, &tegra_emc_debug_max_rate_fops); in tegra_emc_debugfs_init()
980 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); in emc_icc_set() local
988 * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data in emc_icc_set()
989 * is sampled on both clock edges. This means that EMC clock rate in emc_icc_set()
992 dram_data_bus_width_bytes = emc->dram_bus_width / 8; in emc_icc_set()
996 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); in emc_icc_set()
1003 static int tegra_emc_interconnect_init(struct tegra_emc *emc) in tegra_emc_interconnect_init() argument
1009 emc->mc = devm_tegra_memory_controller_get(emc->dev); in tegra_emc_interconnect_init()
1010 if (IS_ERR(emc->mc)) in tegra_emc_interconnect_init()
1011 return PTR_ERR(emc->mc); in tegra_emc_interconnect_init()
1013 soc = emc->mc->soc; in tegra_emc_interconnect_init()
1015 emc->provider.dev = emc->dev; in tegra_emc_interconnect_init()
1016 emc->provider.set = emc_icc_set; in tegra_emc_interconnect_init()
1017 emc->provider.data = &emc->provider; in tegra_emc_interconnect_init()
1018 emc->provider.aggregate = soc->icc_ops->aggregate; in tegra_emc_interconnect_init()
1019 emc->provider.xlate_extended = emc_of_icc_xlate_extended; in tegra_emc_interconnect_init()
1021 icc_provider_init(&emc->provider); in tegra_emc_interconnect_init()
1031 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1046 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1048 err = icc_provider_register(&emc->provider); in tegra_emc_interconnect_init()
1055 icc_nodes_remove(&emc->provider); in tegra_emc_interconnect_init()
1057 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); in tegra_emc_interconnect_init()
1069 struct tegra_emc *emc = data; in devm_tegra_emc_unreg_clk_notifier() local
1071 clk_notifier_unregister(emc->clk, &emc->clk_nb); in devm_tegra_emc_unreg_clk_notifier()
1074 static int tegra_emc_init_clk(struct tegra_emc *emc) in tegra_emc_init_clk() argument
1078 tegra20_clk_set_emc_round_callback(emc_round_rate, emc); in tegra_emc_init_clk()
1080 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, in tegra_emc_init_clk()
1085 emc->clk = devm_clk_get(emc->dev, NULL); in tegra_emc_init_clk()
1086 if (IS_ERR(emc->clk)) { in tegra_emc_init_clk()
1087 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); in tegra_emc_init_clk()
1088 return PTR_ERR(emc->clk); in tegra_emc_init_clk()
1091 err = clk_notifier_register(emc->clk, &emc->clk_nb); in tegra_emc_init_clk()
1093 dev_err(emc->dev, "failed to register clk notifier: %d\n", err); in tegra_emc_init_clk()
1097 err = devm_add_action_or_reset(emc->dev, in tegra_emc_init_clk()
1098 devm_tegra_emc_unreg_clk_notifier, emc); in tegra_emc_init_clk()
1108 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_devfreq_target() local
1121 return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ); in tegra_emc_devfreq_target()
1127 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_devfreq_get_dev_status() local
1130 writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL); in tegra_emc_devfreq_get_dev_status()
1133 * busy_time: number of clocks EMC request was accepted in tegra_emc_devfreq_get_dev_status()
1136 stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT); in tegra_emc_devfreq_get_dev_status()
1137 stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS); in tegra_emc_devfreq_get_dev_status()
1138 stat->current_frequency = clk_get_rate(emc->clk); in tegra_emc_devfreq_get_dev_status()
1141 writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL); in tegra_emc_devfreq_get_dev_status()
1142 writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL); in tegra_emc_devfreq_get_dev_status()
1153 static int tegra_emc_devfreq_init(struct tegra_emc *emc) in tegra_emc_devfreq_init() argument
1164 emc->ondemand_data.upthreshold = 20; in tegra_emc_devfreq_init()
1171 writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); in tegra_emc_devfreq_init()
1172 writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); in tegra_emc_devfreq_init()
1173 writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); in tegra_emc_devfreq_init()
1175 devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile, in tegra_emc_devfreq_init()
1177 &emc->ondemand_data); in tegra_emc_devfreq_init()
1179 dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq); in tegra_emc_devfreq_init()
1190 struct tegra_emc *emc; in tegra_emc_probe() local
1199 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1200 if (!emc) in tegra_emc_probe()
1203 mutex_init(&emc->rate_lock); in tegra_emc_probe()
1204 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; in tegra_emc_probe()
1205 emc->dev = &pdev->dev; in tegra_emc_probe()
1207 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1208 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1209 return PTR_ERR(emc->regs); in tegra_emc_probe()
1211 err = emc_setup_hw(emc); in tegra_emc_probe()
1215 np = tegra_emc_find_node_by_ram_code(emc); in tegra_emc_probe()
1217 err = tegra_emc_load_timings_from_dt(emc, np); in tegra_emc_probe()
1224 dev_name(&pdev->dev), emc); in tegra_emc_probe()
1230 err = tegra_emc_init_clk(emc); in tegra_emc_probe()
1240 platform_set_drvdata(pdev, emc); in tegra_emc_probe()
1241 tegra_emc_rate_requests_init(emc); in tegra_emc_probe()
1242 tegra_emc_debugfs_init(emc); in tegra_emc_probe()
1243 tegra_emc_interconnect_init(emc); in tegra_emc_probe()
1244 tegra_emc_devfreq_init(emc); in tegra_emc_probe()
1257 { .compatible = "nvidia,tegra20-emc", },
1265 .name = "tegra20-emc",
1274 MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver");