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/linux-6.12.1/Documentation/devicetree/bindings/usb/
Daspeed,usb-vhub.yaml16 the Virtual Hub's downstream USB devices.
19 revisions. AST2400 and AST2500 Virtual Hub supports 5 downstream devices
20 and 15 generic endpoints, while AST2600 Virtual Hub supports 7 downstream
39 aspeed,vhub-downstream-ports:
40 description: Number of downstream ports supported by the Virtual Hub
107 - aspeed,vhub-downstream-ports
120 aspeed,vhub-downstream-ports = <5>;
Drealtek,rts5411.yaml46 1st downstream facing USB port
51 2nd downstream facing USB port
56 3rd downstream facing USB port
61 4th downstream facing USB port
/linux-6.12.1/drivers/pci/pcie/
DKconfig11 Management Events, and Downstream Port Containment.
131 bool "PCI Express Downstream Port Containment support"
134 This enables PCI Express Downstream Port Containment (DPC)
135 driver support. DPC events from Root and Downstream ports
154 in the Downstream Port Containment Related Enhancements ECN to
Daspm.c114 * on the downstream component before the upstream. So, don't attempt to in pci_restore_aspm_l1ss_state()
115 * restore either until we are at the downstream component. in pci_restore_aspm_l1ss_state()
147 * Disable L1.2 on this downstream endpoint device first, followed in pci_restore_aspm_l1ss_state()
196 #define PCIE_LINK_STATE_L0S_DW BIT(1) /* Downstream direction L0s state */
209 struct pci_dev *downstream; /* Downstream component, function 0 */ member
400 /* Check downstream component if bit Slot Clock Configuration is 1 */ in pcie_aspm_configure_common_clock()
430 /* Configure downstream component, all functions */ in pcie_aspm_configure_common_clock()
587 /* Check downstream direction L0s latency */ in pcie_aspm_check_latency()
618 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_calc_l12_info()
650 * downstream devices report (via LTR) that they can tolerate at in aspm_calc_l12_info()
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Dportdrv.h21 #define PCIE_PORT_SERVICE_DPC_SHIFT 3 /* Downstream Port Containment */
59 struct pci_dev *port; /* Root/Upstream/Downstream Port */
/linux-6.12.1/drivers/thunderbolt/
Dtb.c517 /* Find the downstream USB4 port that leads to this router */ in tb_find_first_usb3_tunnel()
519 /* Find the corresponding host router USB3 downstream port */ in tb_find_first_usb3_tunnel()
534 * @consumed_down: Consumed downstream bandwidth (Mb/s)
583 * @consumed_down: Consumed downstream bandwidth (Mb/s)
603 bool downstream; in tb_consumed_dp_bandwidth() local
652 downstream = tb_port_path_direction_downstream(src_port, dst_port); in tb_consumed_dp_bandwidth()
654 if (downstream) in tb_consumed_dp_bandwidth()
666 bool downstream = tb_port_path_direction_downstream(src_port, dst_port); in tb_asym_supported() local
670 width = downstream ? TB_LINK_WIDTH_ASYM_RX : TB_LINK_WIDTH_ASYM_TX; in tb_asym_supported()
672 width = downstream ? TB_LINK_WIDTH_ASYM_TX : TB_LINK_WIDTH_ASYM_RX; in tb_asym_supported()
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Dacpi.c44 /* Check that this matches a PCIe root/downstream port. */ in tb_acpi_add_link()
291 * Device routers exists under the downstream facing USB4 port in tb_acpi_switch_find_companion()
321 * Device (DFP0) // Downstream port _ADR == lane 0 adapter in tb_acpi_find_companion()
324 * Device (DFP1) // Downstream port _ADR == lane 0 adapter number in tb_acpi_find_companion()
Dlc.c51 * tb_lc_reset_port() - Trigger downstream port reset through LC
54 * Triggers downstream port reset through link controller registers.
185 * @port: Switch downstream port connected to another host
197 * @port: Switch downstream port that was connected to another host
211 * sleep. Should be called for those downstream lane adapters that were
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls2080a.dtsi141 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
149 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
157 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
165 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
/linux-6.12.1/drivers/firmware/efi/
Dcper_cxl.c34 "Restricted CXL Host Downstream Port",
39 "CXL Downstream Switch Port",
49 RCH_DP, /* Restricted CXL Host Downstream Port */
54 DSP, /* CXL Downstream Switch Port */
/linux-6.12.1/include/uapi/linux/usb/
Dcharger.h11 * SDP (Standard Downstream Port)
13 * CDP (Charging Downstream Port)
/linux-6.12.1/arch/arm/mach-omap2/
Dclockdomain.c938 * into active or idle states, as needed by downstream clocks. If the
939 * clockdomain has any downstream clocks enabled in the clock
980 * active or idle states, as needed by downstream clocks. If the
981 * clockdomain has any downstream clocks enabled in the clock
998 * downstream clocks enabled in the clock framework, wkdep/sleepdep
1036 * downstream clocks enabled in the clock framework, wkdep/sleepdep
1111 * clkdm_clk_enable - add an enabled downstream clock to this clkdm
1113 * @unused: struct clk * of the enabled downstream clock
1152 * clkdm_clk_disable - remove an enabled downstream clock from this clkdm
1154 * @clk: struct clk * of the disabled downstream clock
[all …]
/linux-6.12.1/include/linux/
Di2c-atr.h66 * i2c_atr_add_adapter - Create a child ("downstream") I2C bus.
76 * devices on the downstream bus will result in calls to the
93 * i2c_atr_del_adapter - Remove a child ("downstream") I2C bus added by
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Di2c-atr.yaml14 ("upstream") port and N I2C master child ("downstream") ports, and
15 forwards transactions from upstream to the appropriate downstream port
Di2c-mux-ltc4306.txt24 - ltc,downstream-accelerators-enable: Enables the rise time accelerators
25 on the downstream port.
/linux-6.12.1/Documentation/ABI/testing/
Dusb-charger-uevent14 USB_CHARGER_SDP_TYPE Standard Downstream Port
15 USB_CHARGER_CDP_TYPE Charging Downstream Port
Dsysfs-bus-usb-lvstest16 Set "U1 timeout" for the downstream port where Link Layer
24 Set "U2 timeout" for the downstream port where Link Layer
/linux-6.12.1/drivers/media/pci/cx88/
Dcx88-reg.h213 #define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream
215 #define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream)
433 #define MO_TS_DMA 0x330000 // {64}RWp Transport stream downstream
451 #define MO_VIPD_DMA 0x340000 // {64}RWp VIP downstream
461 #define MO_VIPD_CNTRL 0x340050 // VIP downstream control #2
462 #define MO_VIPD_LNGTH 0x340054 // VIP downstream line length
519 #define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream
522 #define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2
523 #define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length
/linux-6.12.1/drivers/clk/sophgo/
Dclk-sg2042-clkgen.c423 * from top to bottom, from upstream to downstream. Read TRM for details.
604 /* downstream of div_50m_a53 */
646 /* downstream of div_top_axi0 */
681 /* upon are gate clocks directly downstream of muxes */
683 /* downstream of clk_div_top_rp_cmn_div2 */
691 * downstream of clk_gate_rp_cpu_normal
707 /* downstream of div_50m_a53 */
727 /* gate clocks downstream from div clocks one-to-one */
746 /* downstream of clk_div_top_axi0 */
773 /* downstream of DIV clocks which are sourced from clk_div_top_axi0 */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/power/supply/
Dgpio-charger.yaml27 - usb-sdp # USB standard downstream port
29 - usb-cdp # USB charging downstream port
/linux-6.12.1/Documentation/admin-guide/perf/
Dhisi-pcie-pmu.rst9 all Endpoints downstream these Root Ports.
66 PMU could only monitor the performance of traffic downstream target Root
67 Ports or downstream target Endpoint. PCIe PMU driver support "port" and
/linux-6.12.1/drivers/net/ipa/data/
Dipa_data-v3.1.c265 .min = 5, .max = 5, /* 3 downstream */
268 .min = 5, .max = 5, /* 7 downstream */
331 .min = 3, .max = 3, /* 2 downstream */
337 .min = 1, .max = 1, /* 0 downstream */
339 /* IPA_RSRC_GROUP_DST_DMA uses 2 downstream */
/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dfsl,imx8qxp-pxl2dpi.yaml37 A phandle which points to companion PXL2DPI which is used by downstream
50 description: The PXL2DPI output port node to downstream bridge.
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dpci.txt32 root port to downstream device and host bridge drivers can do programming
69 downstream of this port are external to the machine. The OS can, for
/linux-6.12.1/drivers/gpu/drm/display/
Ddrm_dp_helper.c793 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
803 * Returns: whether the downstream facing port matches the type.
815 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
820 * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
995 * drm_dp_read_downstream_info() - read DPCD downstream port info if available
998 * @downstream_ports: buffer to store the downstream port info in
1004 * Returns: 0 if either the downstream port info was read successfully or
1005 * there was no downstream info to read, or a negative error code otherwise.
1016 /* No downstream info to read */ in drm_dp_read_downstream_info()
1020 /* Some branches advertise having 0 downstream ports, despite also advertising they have a in drm_dp_read_downstream_info()
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