| /linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hw_dsc.c | 38 static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc) in dpu_hw_dsc_disable() argument
40 struct dpu_hw_blk_reg_map *c = &dsc->hw; in dpu_hw_dsc_disable()
46 struct drm_dsc_config *dsc, in dpu_hw_dsc_config() argument
61 slice_last_group_size = (dsc->slice_width + 2) % 3; in dpu_hw_dsc_config()
66 data |= (dsc->bits_per_pixel << 8); in dpu_hw_dsc_config()
67 data |= (dsc->block_pred_enable << 7); in dpu_hw_dsc_config()
68 data |= (dsc->line_buf_depth << 3); in dpu_hw_dsc_config()
69 data |= (dsc->simple_422 << 2); in dpu_hw_dsc_config()
70 data |= (dsc->convert_rgb << 1); in dpu_hw_dsc_config()
71 data |= dsc->bits_per_component; in dpu_hw_dsc_config()
[all …]
|
| D | dpu_hw_dsc_1_2.c | 88 struct drm_dsc_config *dsc, in dpu_hw_dsc_config_1_2() argument
99 if (!hw_dsc || !dsc) in dpu_hw_dsc_config_1_2()
112 num_active_slice_per_enc = dsc->slice_count; in dpu_hw_dsc_config_1_2()
114 num_active_slice_per_enc = dsc->slice_count / 2; in dpu_hw_dsc_config_1_2()
129 data = (dsc->dsc_version_minor & 0xf) << 28; in dpu_hw_dsc_config_1_2()
130 if (dsc->dsc_version_minor == 0x2) { in dpu_hw_dsc_config_1_2()
131 if (dsc->native_422) in dpu_hw_dsc_config_1_2()
133 if (dsc->native_420) in dpu_hw_dsc_config_1_2()
137 bpp = dsc->bits_per_pixel; in dpu_hw_dsc_config_1_2()
141 if (dsc->native_422 || dsc->native_420) in dpu_hw_dsc_config_1_2()
[all …]
|
| D | dpu_hw_dsc.h | 19 * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
24 * dsc_disable - disable dsc
25 * @hw_dsc: Pointer to dsc context
30 * dsc_config - configures dsc encoder
31 * @hw_dsc: Pointer to dsc context
32 * @dsc: panel dsc parameters
33 * @mode: dsc topology mode to be set
37 struct drm_dsc_config *dsc,
43 * @hw_dsc: Pointer to dsc context
44 * @dsc: panel dsc parameters
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| D | dcn401_dsc.c | 9 #include "dsc/dscc_types.h"
10 #include "dsc/rc_calc.h"
15 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
19 static void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
20 static bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *…
21 static void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_c…
23 //static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config …
24 static void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
25 static void dsc401_disable(struct display_stream_compressor *dsc);
26 static void dsc401_disconnect(struct display_stream_compressor *dsc);
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dsc/dcn35/ |
| D | dcn35_dsc.c | 30 static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);
57 dsc->ctx->logger
59 void dsc35_construct(struct dcn20_dsc *dsc, in dsc35_construct() argument
66 dsc->base.ctx = ctx; in dsc35_construct()
67 dsc->base.inst = inst; in dsc35_construct()
68 dsc->base.funcs = &dcn35_dsc_funcs; in dsc35_construct()
70 dsc->dsc_regs = dsc_regs; in dsc35_construct()
71 dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift); in dsc35_construct()
72 dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask); in dsc35_construct()
74 dsc->max_image_width = 5184; in dsc35_construct()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dsc/ |
| D | dsc.h | 36 /* Input parameters for configuring DSC from the outside of DSC */
47 /* Output parameters for configuring DSC-related part of OPTC */
69 /* DSC encoder capabilities
70 * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
76 uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
101 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
102 …bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cf…
103 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
105 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
107 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
[all …]
|
| D | dc_dsc.c | 28 #include "dsc.h"
35 /* default DSC policy target bitrate limit is 16bpp */
38 /* default DSC policy enables DSC only when needed */
63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
166 const struct display_stream_compressor *dsc,
202 dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__); in dsc_buff_block_size_from_dpcd()
218 dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__); in dsc_line_buff_depth_from_dpcd()
278 dm_error("%s: DPCD DSC throughput mode not recognized.\n", __func__); in dsc_throughput_from_dpcd()
309 dm_error("%s: DPCD DSC bits-per-pixel increment not recognized.\n", __func__); in dsc_bpp_increment_div_from_dpcd()
[all …]
|
| D | Makefile | 11 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))
22 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))
30 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
34 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o macro
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| D | dcn20_dsc.c | 30 #include "dsc/dscc_types.h"
31 #include "dsc/rc_calc.h"
33 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
58 dsc->ctx->logger
69 void dsc2_construct(struct dcn20_dsc *dsc, in dsc2_construct() argument
76 dsc->base.ctx = ctx; in dsc2_construct()
77 dsc->base.inst = inst; in dsc2_construct()
78 dsc->base.funcs = &dcn20_dsc_funcs; in dsc2_construct()
80 dsc->dsc_regs = dsc_regs; in dsc2_construct()
81 dsc->dsc_shift = dsc_shift; in dsc2_construct()
[all …]
|
| D | dcn20_dsc.h | 27 #include "dsc.h"
28 #include "dsc/dscc_types.h"
31 #define TO_DCN20_DSC(dsc)\ argument
32 container_of(dsc, struct dcn20_dsc, base)
566 void dsc_config_log(struct display_stream_compressor *dsc,
569 void dsc_log_pps(struct display_stream_compressor *dsc,
588 void dsc2_construct(struct dcn20_dsc *dsc,
598 bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,
602 void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
603 bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/msm/ |
| D | msm_dsc_helper.h | 5 * Helper methods for MSM-specific DSC calculations that are common between timing engine,
17 * @dsc: Pointer to drm dsc config struct
21 static inline u32 msm_dsc_get_slices_per_intf(const struct drm_dsc_config *dsc, u32 intf_width) in msm_dsc_get_slices_per_intf() argument
23 return DIV_ROUND_UP(intf_width, dsc->slice_width); in msm_dsc_get_slices_per_intf()
28 * @dsc: Pointer to drm dsc config struct
33 static inline u32 msm_dsc_get_bytes_per_line(const struct drm_dsc_config *dsc) in msm_dsc_get_bytes_per_line() argument
35 return dsc->slice_count * dsc->slice_chunk_size; in msm_dsc_get_bytes_per_line()
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| D | dcn314_hwseq.c | 54 #include "dsc.h"
74 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
79 ASSERT(dsc); in update_dsc_on_stream()
88 /* Enable DSC hw block */ in update_dsc_on_stream()
98 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
99 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
101 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream()
112 /* Enable DSC in OPTC */ in update_dsc_on_stream()
113 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
119 /* disable DSC in OPTC */ in update_dsc_on_stream()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/panel/ |
| D | panel-visionox-r66451.c | 184 if (!dsi->dsc) { in visionox_r66451_enable()
185 dev_err(&dsi->dev, "DSC not attached to DSI\n"); in visionox_r66451_enable()
189 drm_dsc_pps_payload_pack(&pps, dsi->dsc); in visionox_r66451_enable()
282 struct drm_dsc_config *dsc; in visionox_r66451_probe() local
289 dsc = devm_kzalloc(dev, sizeof(*dsc), GFP_KERNEL); in visionox_r66451_probe()
290 if (!dsc) in visionox_r66451_probe()
293 /* Set DSC params */ in visionox_r66451_probe()
294 dsc->dsc_version_major = 0x1; in visionox_r66451_probe()
295 dsc->dsc_version_minor = 0x2; in visionox_r66451_probe()
297 dsc->slice_height = 20; in visionox_r66451_probe()
[all …]
|
| D | panel-lg-sw43408.c | 33 struct drm_dsc_config dsc; member
106 drm_dsc_pps_payload_pack(&pps, sw43408->link->dsc); in sw43408_program()
275 /* The panel works only in the DSC mode. Set DSC params. */ in sw43408_probe()
276 ctx->dsc.dsc_version_major = 0x1; in sw43408_probe()
277 ctx->dsc.dsc_version_minor = 0x1; in sw43408_probe()
280 ctx->dsc.slice_height = 16; in sw43408_probe()
281 ctx->dsc.slice_width = 540; in sw43408_probe()
282 ctx->dsc.slice_count = 2; in sw43408_probe()
283 ctx->dsc.bits_per_component = 8; in sw43408_probe()
284 ctx->dsc.bits_per_pixel = 8 << 4; in sw43408_probe()
[all …]
|
| D | panel-raydium-rm692e5.c | 23 struct drm_dsc_config dsc; member
154 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in rm692e5_prepare()
320 /* This panel only supports DSC; unconditionally enable it */ in rm692e5_probe()
321 dsi->dsc = &ctx->dsc; in rm692e5_probe()
324 ctx->dsc.dsc_version_major = 1; in rm692e5_probe()
325 ctx->dsc.dsc_version_minor = 1; in rm692e5_probe()
326 ctx->dsc.slice_height = 60; in rm692e5_probe()
327 ctx->dsc.slice_width = 1224; in rm692e5_probe()
329 ctx->dsc.slice_count = 1224 / ctx->dsc.slice_width; in rm692e5_probe()
330 ctx->dsc.bits_per_component = 8; in rm692e5_probe()
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dsc.yaml | 4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
7 title: mediatek display DSC controller
14 The DSC standard is a specification of the algorithms used for
17 video bit stream. DSC is designed for real-time systems with
24 - mediatek,mt8195-disp-dsc
34 - description: DSC Wrapper Clock
73 compatible = "mediatek,mt8195-disp-dsc";
|
| /linux-6.12.1/include/drm/display/ |
| D | drm_dsc.h | 13 /* VESA Display Stream Compression DSC 1.2 constants */
21 /* DSC Rate Control Constants */
27 /* DSC PPS constants and macros */
45 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
47 * This defines different rate control parameters used by the DSC engine
67 * struct drm_dsc_config - Parameters required to configure DSC
89 * @slice_count: Number fo slices per line used by the DSC encoder
239 * @dsc_version_minor: DSC minor version
243 * @dsc_version_major: DSC major version
276 * The VESA DSC standard defines picture parameter set (PPS) which display
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_vdsc.c | 49 /* There's no pipe A DSC engine on ICL */ in is_pipe_dsc()
69 * We are using the method provided in DSC 1.2a C-Model in codec_main.c
70 * Above method use a common formula to derive values for any combination of DSC
98 * According to DSC 1.2 spec in Section 4.1 if native_420 is set: in calculate_rc_params()
266 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
267 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); in intel_dsc_compute_params()
273 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
283 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 in intel_dsc_compute_params()
298 vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16; in intel_dsc_compute_params()
301 * According to DSC 1.2 specs in Section 4.1 if native_420 is set in intel_dsc_compute_params()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_debugfs.c | 37 #include "dsc.h"
1167 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1169 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1327 /* function: Read link's DSC & FEC capabilities
1370 * enable DSC on the sink device or on MST branch in dp_dsc_fec_support_show()
1513 /* function: read DSC status on the connector
1516 * returns current status of DSC clock on the connector.
1525 * 1 - means that DSC is currently enabled
1526 * 0 - means that DSC is disabled
1534 struct display_stream_compressor *dsc; in dp_dsc_clock_en_read() local
[all …]
|
| D | amdgpu_dm_mst_types.c | 237 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 in validate_dsc_caps_on_connector()
244 * because it only check the dsc/fec caps of the "port variable" and not the dock in validate_dsc_caps_on_connector()
246 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display in validate_dsc_caps_on_connector()
855 params[i].timing->flags.DSC = 1; in set_dsc_configs_from_fairness_vars()
868 params[i].timing->flags.DSC = 0; in set_dsc_configs_from_fairness_vars()
881 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n", in set_dsc_configs_from_fairness_vars()
882 params[i].timing->flags.DSC, in set_dsc_configs_from_fairness_vars()
1076 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index); in try_disable_dsc()
1104 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n", in log_dsc_params()
1146 stream->timing.flags.DSC = 0; in compute_mst_dsc_configs_for_link()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/msm/dsi/ |
| D | dsi_host.c | 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
159 struct drm_dsc_config *dsc; member
521 * @dsc: DRM DSC configuration for this DSI output
528 * - For VIDEO mode they are not compressed by DSC and are passed as is.
538 const struct drm_dsc_config *dsc) in dsi_adjust_pclk_for_compression() argument
540 int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), in dsi_adjust_pclk_for_compression()
541 dsc->bits_per_component * 3); in dsi_adjust_pclk_for_compression()
549 const struct drm_dsc_config *dsc, bool is_bonded_dsi) in dsi_get_pclk_rate() argument
555 if (dsc) in dsi_get_pclk_rate()
556 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc); in dsi_get_pclk_rate()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/display/ |
| D | drm_dsc_helper.c | 21 * DOC: dsc helpers
24 * Compression (DSC) used to compress the pixel bits before sending it on
25 * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing
30 * Display Stream Compression standard required for DSC on Display Port/eDP or
37 * @pps_header: Secondary data packet header for DSC Picture
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
85 * Bitwise struct for DSC Picture Parameter Set. This is defined
88 * DSC Configuration data filled by driver as defined by
91 * DSC source device sends a picture parameter set (PPS) containing the
93 * populates the DSC PPS struct using the DSC configuration parameters in
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn35/ |
| D | dcn35_hwseq.c | 54 #include "dsc.h"
322 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
329 ASSERT(dsc); in update_dsc_on_stream()
339 if (!dsc) { in update_dsc_on_stream()
340 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
344 if (dsc->funcs->dsc_read_state) { in update_dsc_on_stream()
345 dsc->funcs->dsc_read_state(dsc, &dsc_state); in update_dsc_on_stream()
347 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
351 /* Enable DSC hw block */ in update_dsc_on_stream()
361 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/ |
| D | link_dpms.c | 54 #include "dsc.h"
740 static void dsc_optc_config_log(struct display_stream_compressor *dsc, in dsc_optc_config_log() argument
747 DC_LOGGER_INIT(dsc->ctx->logger); in dsc_optc_config_log()
749 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC in dsc_optc_config_log()
775 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
783 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream() local
793 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger in link_set_dsc_on_stream()
800 DC_LOGGER_INIT(dsc->ctx->logger); in link_set_dsc_on_stream()
810 /* Enable DSC hw block */ in link_set_dsc_on_stream()
821 dccg->funcs->set_dto_dscclk(dccg, dsc->inst); in link_set_dsc_on_stream()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| D | dcn32_hwseq.c | 48 #include "dsc.h"
89 DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst); in dcn32_dsc_pg_control()
1009 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dcn32_update_dsc_on_stream() local
1019 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger in dcn32_update_dsc_on_stream()
1027 ASSERT(dsc); in dcn32_update_dsc_on_stream()
1037 if (!dsc) { in dcn32_update_dsc_on_stream()
1038 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in dcn32_update_dsc_on_stream()
1042 if (dsc->funcs->dsc_read_state) { in dcn32_update_dsc_on_stream()
1043 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dcn32_update_dsc_on_stream()
1045 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in dcn32_update_dsc_on_stream()
[all …]
|