49 	/* There's no pipe A DSC engine on ICL */  in is_pipe_dsc()
69  * We are using the method provided in DSC 1.2a C-Model in codec_main.c
70  * Above method use a common formula to derive values for any combination of DSC
98 	 * According to DSC 1.2 spec in Section 4.1 if native_420 is set:  in calculate_rc_params()
266 	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;  in intel_dsc_compute_params()
267 	u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);  in intel_dsc_compute_params()
273 					     pipe_config->dsc.slice_count);  in intel_dsc_compute_params()
283 	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0  in intel_dsc_compute_params()
298 	vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;  in intel_dsc_compute_params()
301 	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set  in intel_dsc_compute_params()
376 	return crtc_state->dsc.dsc_split ? 2 : 1;  in intel_dsc_get_vdsc_per_pipe()
430 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dsc_pps_configure()
686 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dsc_dsi_pps_write()
692 	if (!crtc_state->dsc.compression_enable)  in intel_dsc_dsi_pps_write()
709 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dsc_dp_pps_write()
712 	if (!crtc_state->dsc.compression_enable)  in intel_dsc_dp_pps_write()
718 	/* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */  in intel_dsc_dp_pps_write()
744 	if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {  in intel_uncompressed_joiner_enable()
762 	if (!crtc_state->dsc.compression_enable)  in intel_dsc_enable()
787 	if (old_crtc_state->dsc.compression_enable ||  in intel_dsc_disable()
839 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dsc_get_pps_config()
865 	crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;  in intel_dsc_get_pps_config()
962 	crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;  in intel_dsc_get_config()
963 	if (!crtc_state->dsc.compression_enable)  in intel_dsc_get_config()
966 	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&  in intel_dsc_get_config()
978 			  "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n",  in intel_vdsc_dump_state()
979 			  FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),  in intel_vdsc_dump_state()
980 			  crtc_state->dsc.slice_count,  in intel_vdsc_dump_state()
981 			  str_yes_no(crtc_state->dsc.dsc_split));  in intel_vdsc_dump_state()
987 	if (!crtc_state->dsc.compression_enable)  in intel_vdsc_state_dump()
991 	drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);  in intel_vdsc_state_dump()