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/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dsb.c40 * ins_start_offset will help to store start dword of the dsb
51 * DOC: DSB
53 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
54 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
55 * engine that can be programmed to download the DSB from memory.
58 * faster. DSB Support added from Gen12 Intel graphics based platform.
60 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
63 * DSB HW can support only register writes (both indexed and direct MMIO
64 * writes). There are no registers reads possible with DSB HW engine.
67 /* DSB opcodes. */
[all …]
Dintel_dsb.h33 void intel_dsb_finish(struct intel_dsb *dsb);
34 void intel_dsb_cleanup(struct intel_dsb *dsb);
35 void intel_dsb_reg_write(struct intel_dsb *dsb,
37 void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
39 void intel_dsb_noop(struct intel_dsb *dsb, int count);
40 void intel_dsb_nonpost_start(struct intel_dsb *dsb);
41 void intel_dsb_nonpost_end(struct intel_dsb *dsb);
43 struct intel_dsb *dsb,
46 struct intel_dsb *dsb,
49 struct intel_dsb *dsb,
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwell/
Dfrontend.json11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
52 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
57 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
62 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
72 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
87 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
92 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellx/
Dfrontend.json11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
52 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
57 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
62 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
72 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
87 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
92 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellde/
Dfrontend.json11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
15 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
47 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
52 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
57 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
62 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
72 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
82 …s the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
87 …n uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
92 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting inc…
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/ivytown/
Dfrontend.json12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
16 "PublicDescription": "Number of DSB to MITE switches.",
21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
25 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
30 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
34 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/ivybridge/
Dfrontend.json12 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
16 "PublicDescription": "Number of DSB to MITE switches.",
21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
25 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
30 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
34 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
66 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
71 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
76 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
81 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
[all …]
/linux-6.12.1/drivers/hwtracing/coresight/
Dcoresight-tpdm.c38 drvdata->dsb->edge_ctrl[tpdm_attr->idx]); in tpdm_simple_dataset_show()
43 drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show()
48 drvdata->dsb->trig_patt[tpdm_attr->idx]); in tpdm_simple_dataset_show()
53 drvdata->dsb->trig_patt_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show()
58 drvdata->dsb->patt_val[tpdm_attr->idx]); in tpdm_simple_dataset_show()
63 drvdata->dsb->patt_mask[tpdm_attr->idx]); in tpdm_simple_dataset_show()
68 drvdata->dsb->msr[tpdm_attr->idx]); in tpdm_simple_dataset_show()
118 drvdata->dsb->trig_patt[tpdm_attr->idx] = val; in tpdm_simple_dataset_store()
124 drvdata->dsb->trig_patt_mask[tpdm_attr->idx] = val; in tpdm_simple_dataset_store()
130 drvdata->dsb->patt_val[tpdm_attr->idx] = val; in tpdm_simple_dataset_store()
[all …]
Dcoresight-tpdm.h41 /* MAX number of DSB MSR */
44 /* DSB Subunit Registers */
55 /* Enable bit for DSB subunit */
57 /* Enable bit for DSB subunit perfmance mode */
59 /* Enable bit for DSB subunit trigger type */
61 /* Data bits for DSB high performace mode */
63 /* Data bits for DSB test mode */
66 /* Enable bit for DSB subunit pattern timestamp */
68 /* Enable bit for DSB subunit trigger timestamp */
70 /* Bit for DSB subunit pattern type */
[all …]
/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-tpdm30 (RW) Set/Get the trigger type of the DSB for tpdm.
33 0 : Set the DSB trigger type to false
34 1 : Set the DSB trigger type to true
41 (RW) Set/Get the trigger timestamp of the DSB for tpdm.
44 0 : Set the DSB trigger type to false
45 1 : Set the DSB trigger type to true
52 (RW) Set/Get the programming mode of the DSB for tpdm.
66 (RW) Set/Get the index number of the edge detection for the DSB
103 Read a set of the edge control value of the DSB in TPDM.
110 Read a set of the edge control mask of the DSB in TPDM.
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/skylakex/
Dfrontend.json21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
39 "BriefDescription": "Retired Instructions who experienced DSB miss.",
46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is…
303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/skylake/
Dfrontend.json21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
39 "BriefDescription": "Retired Instructions who experienced DSB miss.",
46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is…
303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/cascadelakex/
Dfrontend.json21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
25 …ber of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Dec…
30 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
34 …DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because o…
39 "BriefDescription": "Retired Instructions who experienced DSB miss.",
46 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
51 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
58 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
298 …"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 or more Uops [This event is…
303 …delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includ…
[all …]
/linux-6.12.1/arch/arm64/kvm/hyp/nvhe/
Dtlb.c35 * CPUs, for which a dsb(DOMAIN-st) is what we need, DOMAIN in enter_vmid_context()
41 * registers out of context, for which dsb(nsh) is enough in enter_vmid_context()
43 * The composition of these two barriers is a dsb(DOMAIN), and in enter_vmid_context()
49 dsb(nsh); in enter_vmid_context()
51 dsb(ish); in enter_vmid_context()
170 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
172 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
200 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
202 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
227 dsb(ish); in __kvm_tlb_flush_vmid_range()
[all …]
/linux-6.12.1/arch/arm64/kvm/hyp/vhe/
Dtlb.c97 dsb(ishst); in __kvm_tlb_flush_vmid_ipa()
116 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
118 dsb(ish); in __kvm_tlb_flush_vmid_ipa()
129 dsb(nshst); in __kvm_tlb_flush_vmid_ipa_nsh()
148 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
150 dsb(nsh); in __kvm_tlb_flush_vmid_ipa_nsh()
169 dsb(ishst); in __kvm_tlb_flush_vmid_range()
177 dsb(ish); in __kvm_tlb_flush_vmid_range()
179 dsb(ish); in __kvm_tlb_flush_vmid_range()
189 dsb(ishst); in __kvm_tlb_flush_vmid()
[all …]
/linux-6.12.1/fs/erofs/
Dsuper.c58 struct erofs_super_block *dsb; in erofs_superblock_csum_verify() local
64 dsb = kmemdup(sbdata + EROFS_SUPER_OFFSET, len, GFP_KERNEL); in erofs_superblock_csum_verify()
65 if (!dsb) in erofs_superblock_csum_verify()
68 expected_crc = le32_to_cpu(dsb->checksum); in erofs_superblock_csum_verify()
69 dsb->checksum = 0; in erofs_superblock_csum_verify()
71 crc = crc32c(~0, dsb, len); in erofs_superblock_csum_verify()
72 kfree(dsb); in erofs_superblock_csum_verify()
149 struct erofs_super_block *dsb) in z_erofs_parse_cfgs() argument
151 if (!dsb->u1.available_compr_algs) in z_erofs_parse_cfgs()
212 struct erofs_super_block *dsb) in erofs_scan_devices() argument
[all …]
/linux-6.12.1/arch/arm64/include/asm/
Dtlbflush.h35 "dsb ish\n tlbi " #op, \
43 "dsb ish\n tlbi " #op ", %0", \
193 * DSB ISHST // Ensure prior page-table updates have completed
195 * DSB ISH // Ensure the TLB invalidation has completed
259 dsb(nshst); in local_flush_tlb_all()
261 dsb(nsh); in local_flush_tlb_all()
267 dsb(ishst); in flush_tlb_all()
269 dsb(ish); in flush_tlb_all()
277 dsb(ishst); in flush_tlb_mm()
281 dsb(ish); in flush_tlb_mm()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/arm/
Dqcom,coresight-tpdm.yaml14 Single Bit (DSB). It performs data collection in the data producing clock
47 qcom,dsb-element-bits:
49 Specifies the DSB(Discrete Single Bit) element size supported by
51 is enabled. DSB element size currently only supports 32-bit and 64-bit.
62 qcom,dsb-msrs-num:
64 Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
66 or set to 0, it means this DSB TPDM doesn't support MSR.
113 qcom,dsb-element-bits = <32>;
114 qcom,dsb-msrs-num = <16>;
/linux-6.12.1/tools/perf/pmu-events/arch/x86/sandybridge/
Dfrontend.json11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
23 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod…
28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
36 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
44 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
105 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
114 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/jaketown/
Dfrontend.json11 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.",
19 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
23 …t counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decod…
28 …"BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exce…
36 …escription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buff…
44 … "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.",
69 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.",
78 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.",
105 … uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
114 …ion": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
/linux-6.12.1/arch/arm/include/asm/
Dbarrier.h20 #define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory") macro
31 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro
38 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro
43 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ macro
58 #define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0)
60 #define __arm_heavy_mb(x...) dsb(x)
65 #define rmb() dsb()
/linux-6.12.1/arch/arm/mach-omap2/
Dsleep43xx.S99 dsb
114 dsb
116 dsb
138 dsb
140 dsb
262 dsb
388 dsb
390 dsb
394 dsb
396 dsb
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/rocketlake/
Dfrontend.json21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
36 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
41 "BriefDescription": "Retired Instructions who experienced DSB miss.",
48 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
53 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
60 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
299 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
304 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/icelake/
Dfrontend.json21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
36 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
41 "BriefDescription": "Retired Instructions who experienced DSB miss.",
48 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
53 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
60 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
299 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
304 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/tigerlake/
Dfrontend.json21 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
32 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
36 …DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded b…
41 "BriefDescription": "Retired Instructions who experienced DSB miss.",
48 …"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. …
53 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
60 …tical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls we…
299 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
304 …s uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
[all …]

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