Lines Matching full:dsb
40 * ins_start_offset will help to store start dword of the dsb
51 * DOC: DSB
53 * A DSB (Display State Buffer) is a queue of MMIO instructions in the memory
54 * which can be offloaded to DSB HW in Display Controller. DSB HW is a DMA
55 * engine that can be programmed to download the DSB from memory.
58 * faster. DSB Support added from Gen12 Intel graphics based platform.
60 * DSB's can access only the pipe, plane, and transcoder Data Island Packet
63 * DSB HW can support only register writes (both indexed and direct MMIO
64 * writes). There are no registers reads possible with DSB HW engine.
67 /* DSB opcodes. */
174 static bool assert_dsb_has_room(struct intel_dsb *dsb) in assert_dsb_has_room() argument
176 struct intel_crtc *crtc = dsb->crtc; in assert_dsb_has_room()
180 return !drm_WARN(display->drm, dsb->free_pos > dsb->size - 2, in assert_dsb_has_room()
181 "[CRTC:%d:%s] DSB %d buffer overflow\n", in assert_dsb_has_room()
182 crtc->base.base.id, crtc->base.name, dsb->id); in assert_dsb_has_room()
185 static void intel_dsb_dump(struct intel_dsb *dsb) in intel_dsb_dump() argument
187 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_dump()
191 drm_dbg_kms(display->drm, "[CRTC:%d:%s] DSB %d commands {\n", in intel_dsb_dump()
192 crtc->base.base.id, crtc->base.name, dsb->id); in intel_dsb_dump()
193 for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4) in intel_dsb_dump()
196 intel_dsb_buffer_read(&dsb->dsb_buf, i), in intel_dsb_dump()
197 intel_dsb_buffer_read(&dsb->dsb_buf, i + 1), in intel_dsb_dump()
198 intel_dsb_buffer_read(&dsb->dsb_buf, i + 2), in intel_dsb_dump()
199 intel_dsb_buffer_read(&dsb->dsb_buf, i + 3)); in intel_dsb_dump()
209 static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) in intel_dsb_emit() argument
211 if (!assert_dsb_has_room(dsb)) in intel_dsb_emit()
215 dsb->free_pos = ALIGN(dsb->free_pos, 2); in intel_dsb_emit()
217 dsb->ins_start_offset = dsb->free_pos; in intel_dsb_emit()
219 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, ldw); in intel_dsb_emit()
220 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, udw); in intel_dsb_emit()
223 static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, in intel_dsb_prev_ins_is_write() argument
233 if (dsb->free_pos == 0) in intel_dsb_prev_ins_is_write()
236 prev_opcode = intel_dsb_buffer_read(&dsb->dsb_buf, in intel_dsb_prev_ins_is_write()
237 dsb->ins_start_offset + 1) & ~DSB_REG_VALUE_MASK; in intel_dsb_prev_ins_is_write()
238 prev_reg = intel_dsb_buffer_read(&dsb->dsb_buf, in intel_dsb_prev_ins_is_write()
239 dsb->ins_start_offset + 1) & DSB_REG_VALUE_MASK; in intel_dsb_prev_ins_is_write()
244 static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg) in intel_dsb_prev_ins_is_mmio_write() argument
247 return intel_dsb_prev_ins_is_write(dsb, in intel_dsb_prev_ins_is_mmio_write()
253 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) in intel_dsb_prev_ins_is_indexed_write() argument
255 return intel_dsb_prev_ins_is_write(dsb, in intel_dsb_prev_ins_is_indexed_write()
261 * intel_dsb_reg_write() - Emit register wriite to the DSB context
262 * @dsb: DSB context
267 * buffer of DSB.
269 void intel_dsb_reg_write(struct intel_dsb *dsb, in intel_dsb_reg_write() argument
285 * As every instruction is 8 byte aligned the index of dsb instruction in intel_dsb_reg_write()
290 if (!intel_dsb_prev_ins_is_mmio_write(dsb, reg) && in intel_dsb_reg_write()
291 !intel_dsb_prev_ins_is_indexed_write(dsb, reg)) { in intel_dsb_reg_write()
292 intel_dsb_emit(dsb, val, in intel_dsb_reg_write()
297 if (!assert_dsb_has_room(dsb)) in intel_dsb_reg_write()
301 if (intel_dsb_prev_ins_is_mmio_write(dsb, reg)) { in intel_dsb_reg_write()
302 u32 prev_val = intel_dsb_buffer_read(&dsb->dsb_buf, in intel_dsb_reg_write()
303 dsb->ins_start_offset + 0); in intel_dsb_reg_write()
305 intel_dsb_buffer_write(&dsb->dsb_buf, in intel_dsb_reg_write()
306 dsb->ins_start_offset + 0, 1); /* count */ in intel_dsb_reg_write()
307 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 1, in intel_dsb_reg_write()
310 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 2, prev_val); in intel_dsb_reg_write()
312 dsb->free_pos++; in intel_dsb_reg_write()
315 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val); in intel_dsb_reg_write()
317 old_val = intel_dsb_buffer_read(&dsb->dsb_buf, dsb->ins_start_offset); in intel_dsb_reg_write()
318 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset, old_val + 1); in intel_dsb_reg_write()
321 if (dsb->free_pos & 0x1) in intel_dsb_reg_write()
322 intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0); in intel_dsb_reg_write()
335 void intel_dsb_reg_write_masked(struct intel_dsb *dsb, in intel_dsb_reg_write_masked() argument
338 intel_dsb_emit(dsb, val, in intel_dsb_reg_write_masked()
344 void intel_dsb_noop(struct intel_dsb *dsb, int count) in intel_dsb_noop() argument
349 intel_dsb_emit(dsb, 0, in intel_dsb_noop()
353 void intel_dsb_nonpost_start(struct intel_dsb *dsb) in intel_dsb_nonpost_start() argument
355 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_nonpost_start()
358 intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id), in intel_dsb_nonpost_start()
360 intel_dsb_noop(dsb, 4); in intel_dsb_nonpost_start()
363 void intel_dsb_nonpost_end(struct intel_dsb *dsb) in intel_dsb_nonpost_end() argument
365 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_nonpost_end()
368 intel_dsb_reg_write_masked(dsb, DSB_CTRL(pipe, dsb->id), in intel_dsb_nonpost_end()
370 intel_dsb_noop(dsb, 4); in intel_dsb_nonpost_end()
373 static void intel_dsb_emit_wait_dsl(struct intel_dsb *dsb, in intel_dsb_emit_wait_dsl() argument
379 intel_dsb_emit(dsb, lower_32_bits(window), in intel_dsb_emit_wait_dsl()
385 struct intel_dsb *dsb, in intel_dsb_wait_dsl() argument
389 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait_dsl()
398 intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_IN, in intel_dsb_wait_dsl()
401 intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, in intel_dsb_wait_dsl()
408 struct intel_dsb *dsb, in assert_dsl_ok() argument
411 struct intel_crtc *crtc = dsb->crtc; in assert_dsl_ok()
419 "[CRTC:%d:%s] DSB %d bad scanline window wait: %d-%d (vt=%d)\n", in assert_dsl_ok()
420 crtc->base.base.id, crtc->base.name, dsb->id, in assert_dsl_ok()
425 struct intel_dsb *dsb, in intel_dsb_wait_scanline_in() argument
428 assert_dsl_ok(state, dsb, start, end); in intel_dsb_wait_scanline_in()
430 intel_dsb_wait_dsl(state, dsb, in intel_dsb_wait_scanline_in()
436 struct intel_dsb *dsb, in intel_dsb_wait_scanline_out() argument
439 assert_dsl_ok(state, dsb, start, end); in intel_dsb_wait_scanline_out()
441 intel_dsb_wait_dsl(state, dsb, in intel_dsb_wait_scanline_out()
446 static void intel_dsb_align_tail(struct intel_dsb *dsb) in intel_dsb_align_tail() argument
450 tail = dsb->free_pos * 4; in intel_dsb_align_tail()
454 intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, in intel_dsb_align_tail()
457 dsb->free_pos = aligned_tail / 4; in intel_dsb_align_tail()
460 void intel_dsb_finish(struct intel_dsb *dsb) in intel_dsb_finish() argument
462 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_finish()
465 * DSB_FORCE_DEWAKE remains active even after DSB is in intel_dsb_finish()
470 intel_dsb_reg_write(dsb, DSB_PMCTRL(crtc->pipe, dsb->id), 0); in intel_dsb_finish()
471 intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id), in intel_dsb_finish()
474 intel_dsb_align_tail(dsb); in intel_dsb_finish()
476 intel_dsb_buffer_flush_map(&dsb->dsb_buf); in intel_dsb_finish()
514 struct intel_dsb *dsb, in _intel_dsb_chain() argument
519 struct intel_crtc *crtc = dsb->crtc; in _intel_dsb_chain()
523 if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) in _intel_dsb_chain()
530 intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), in _intel_dsb_chain()
533 intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id), in _intel_dsb_chain()
536 intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id), in _intel_dsb_chain()
544 intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id), in _intel_dsb_chain()
549 intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), in _intel_dsb_chain()
552 intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), in _intel_dsb_chain()
557 * Keep DEwake alive via the first DSB, in in _intel_dsb_chain()
560 * DSB won't do its job. in _intel_dsb_chain()
562 intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(pipe, dsb->id), in _intel_dsb_chain()
565 intel_dsb_wait_scanline_out(state, dsb, in _intel_dsb_chain()
572 struct intel_dsb *dsb, in intel_dsb_chain() argument
576 _intel_dsb_chain(state, dsb, chained_dsb, in intel_dsb_chain()
580 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, in _intel_dsb_commit() argument
583 struct intel_crtc *crtc = dsb->crtc; in _intel_dsb_commit()
588 tail = dsb->free_pos * 4; in _intel_dsb_commit()
592 if (is_dsb_busy(display, pipe, dsb->id)) { in _intel_dsb_commit()
593 drm_err(display->drm, "[CRTC:%d:%s] DSB %d is busy\n", in _intel_dsb_commit()
594 crtc->base.base.id, crtc->base.name, dsb->id); in _intel_dsb_commit()
598 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), in _intel_dsb_commit()
601 intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), in _intel_dsb_commit()
602 dsb->chicken); in _intel_dsb_commit()
604 intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), in _intel_dsb_commit()
608 intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), in _intel_dsb_commit()
609 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); in _intel_dsb_commit()
614 intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), in _intel_dsb_commit()
625 intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id), in _intel_dsb_commit()
630 intel_de_write_fw(display, DSB_TAIL(pipe, dsb->id), in _intel_dsb_commit()
631 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + tail); in _intel_dsb_commit()
635 * intel_dsb_commit() - Trigger workload execution of DSB.
636 * @dsb: DSB context
639 * This function is used to do actual write to hardware using DSB.
641 void intel_dsb_commit(struct intel_dsb *dsb, in intel_dsb_commit() argument
644 _intel_dsb_commit(dsb, in intel_dsb_commit()
646 wait_for_vblank ? dsb->hw_dewake_scanline : -1); in intel_dsb_commit()
649 void intel_dsb_wait(struct intel_dsb *dsb) in intel_dsb_wait() argument
651 struct intel_crtc *crtc = dsb->crtc; in intel_dsb_wait()
655 if (wait_for(!is_dsb_busy(display, pipe, dsb->id), 1)) { in intel_dsb_wait()
656 u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); in intel_dsb_wait()
658 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), in intel_dsb_wait()
662 "[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n", in intel_dsb_wait()
663 crtc->base.base.id, crtc->base.name, dsb->id, in intel_dsb_wait()
664 intel_de_read_fw(display, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset, in intel_dsb_wait()
665 intel_de_read_fw(display, DSB_HEAD(pipe, dsb->id)) - offset, in intel_dsb_wait()
666 intel_de_read_fw(display, DSB_TAIL(pipe, dsb->id)) - offset); in intel_dsb_wait()
668 intel_dsb_dump(dsb); in intel_dsb_wait()
672 dsb->free_pos = 0; in intel_dsb_wait()
673 dsb->ins_start_offset = 0; in intel_dsb_wait()
674 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0); in intel_dsb_wait()
676 intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), in intel_dsb_wait()
681 * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
684 * @dsb_id: the DSB engine to use
687 * This function prepare the command buffer which is used to store dsb
691 * DSB context, NULL on failure
700 struct intel_dsb *dsb; in intel_dsb_prepare() local
709 /* TODO: DSB is broken in Xe KMD, so disabling it until fixed */ in intel_dsb_prepare()
713 dsb = kzalloc(sizeof(*dsb), GFP_KERNEL); in intel_dsb_prepare()
714 if (!dsb) in intel_dsb_prepare()
722 if (!intel_dsb_buffer_create(crtc, &dsb->dsb_buf, size)) in intel_dsb_prepare()
727 dsb->id = dsb_id; in intel_dsb_prepare()
728 dsb->crtc = crtc; in intel_dsb_prepare()
729 dsb->size = size / 4; /* in dwords */ in intel_dsb_prepare()
730 dsb->free_pos = 0; in intel_dsb_prepare()
731 dsb->ins_start_offset = 0; in intel_dsb_prepare()
733 dsb->chicken = dsb_chicken(state, crtc); in intel_dsb_prepare()
734 dsb->hw_dewake_scanline = in intel_dsb_prepare()
737 return dsb; in intel_dsb_prepare()
741 kfree(dsb); in intel_dsb_prepare()
744 … "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n", in intel_dsb_prepare()
751 * intel_dsb_cleanup() - To cleanup DSB context.
752 * @dsb: DSB context
754 * This function cleanup the DSB context by unpinning and releasing
757 void intel_dsb_cleanup(struct intel_dsb *dsb) in intel_dsb_cleanup() argument
759 intel_dsb_buffer_cleanup(&dsb->dsb_buf); in intel_dsb_cleanup()
760 kfree(dsb); in intel_dsb_cleanup()
774 drm_err(display->drm, "[CRTC:%d:%s] DSB %d error interrupt: 0x%x\n", in intel_dsb_irq_handler()