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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-pll.yaml68 BWADJ--->
72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
/linux-6.12.1/drivers/clk/
Dclk-k210.c312 u32 bwadj; member
410 reg |= FIELD_PREP(K210_PLL_BWADJ, pll_cfg->bwadj); in k210_pll_enable_hw()
/linux-6.12.1/drivers/crypto/cavium/nitrox/
Dnitrox_csr.h1399 * BWADJ value