| /linux-6.12.1/arch/arm64/kvm/hyp/nvhe/ |
| D | sys_regs.c | 260 * Accessor for AArch32 feature id registers.
262 * The value of these registers is "unknown" according to the spec if AArch32
275 * No support for AArch32 guests, therefore, pKVM has no sanitized copy in pvm_access_id_aarch32()
276 * of AArch32 feature id registers. in pvm_access_id_aarch32()
315 /* Mark the specified system register as an AArch32 feature id register. */
316 #define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 } macro
349 /* AArch64 mappings of the AArch32 ID registers */
351 AARCH32(SYS_ID_PFR0_EL1),
352 AARCH32(SYS_ID_PFR1_EL1),
353 AARCH32(SYS_ID_DFR0_EL1),
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| D | switch.c | 243 * Some guests (e.g., protected VMs) are not be allowed to run in AArch32.
245 * guest from dropping to AArch32 EL0 if implemented by the CPU. If the
250 * Returns false if the guest ran in AArch32 when it shouldn't have, and
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| /linux-6.12.1/arch/arm64/include/asm/ |
| D | ptrace.h | 35 /* AArch32-specific ptrace requests */
45 /* SPSR_ELx bits for exceptions taken from AArch32 */
77 /* AArch32 CPSR bits, as seen in AArch32 */
101 /* sizeof(struct user) for AArch32 */
104 /* Architecturally defined mapping between AArch32 and AArch64 registers */
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| D | kvm_emulate.h | 156 * AArch32 with banked registers.
229 * The layout of SPSR for an AArch32 state is different when observed from an
230 * AArch64 SPSR_ELx or an AArch32 SPSR_*. This function generates the AArch32
236 * - The AArch32 view (SPSR_abt) in section G8.2.126, page G8-6256
237 * - The AArch32 view (SPSR_und) in section G8.2.132, page G8-6280
244 * | 21 | SS | DIT | SS doesn't exist in AArch32 |
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| D | elf.h | 204 /* AArch32 registers. */
214 /* AArch32 EABI. */
264 /* No known properties for AArch32 yet */ in arch_parse_elf_property()
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| D | cpu.h | 68 struct cpuinfo_32bit aarch32; member
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| D | debug-monitors.h | 48 /* AArch32 */
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| D | mmu.h | 10 #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */
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| D | ftrace.h | 155 * Because AArch32 mode does not share the same syscall table with AArch64,
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| /linux-6.12.1/arch/arm64/kvm/hyp/ |
| D | exception.c | 82 * of the inherited bits have the same position in the AArch64/AArch32 SPSR_ELx
83 * layouts, so we don't need to shuffle these for exceptions from AArch32 EL0.
86 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
182 * For the SPSR layout seen from AArch32, see:
186 * For the SPSR_ELx layout for AArch32 seen from AArch64, see:
189 * Here we manipulate the fields in order of the AArch32 SPSR_ELx layout, from
224 // SS does not exist in AArch32, so ignore in get_except32_cpsr()
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| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/ |
| D | instruction.json | 13 …"PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CO…
20 …"PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/…
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| /linux-6.12.1/Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
60 no offset applied and do not sample the instruction set state in AArch32
62 in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
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| /linux-6.12.1/arch/arm64/kernel/ |
| D | kuser32.S | 3 * AArch32 user helpers.
11 * reasons with 32 bit (aarch32) applications that need them.
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| D | traps.c | 464 /* check for AArch32 breakpoint instructions */ in do_el0_undef()
834 [ESR_ELx_EC_SVC32] = "SVC (AArch32)",
835 [ESR_ELx_EC_HVC32] = "HVC (AArch32)",
836 [ESR_ELx_EC_SMC32] = "SMC (AArch32)",
853 [ESR_ELx_EC_FP_EXC32] = "FP (AArch32)",
862 [ESR_ELx_EC_BKPT32] = "BKPT (AArch32)",
863 [ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)",
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| D | sigreturn32.S | 3 * AArch32 sigreturn code.
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| /linux-6.12.1/drivers/firmware/efi/ |
| D | cper-arm.c | 21 "AArch32 general purpose registers",
22 "AArch32 EL1 context registers",
23 "AArch32 EL2 context registers",
24 "AArch32 secure context registers",
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| /linux-6.12.1/lib/raid6/ |
| D | recov_neon_inner.c | 12 * AArch32 does not provide this intrinsic natively because it does not
13 * implement the underlying instruction. AArch32 only provides a 64-bit
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| /linux-6.12.1/arch/arm64/kvm/hyp/include/nvhe/ |
| D | fixed_config.h | 48 * - AArch64 guests only (no support for AArch32 guests):
49 * AArch32 adds complexity in trap handling, emulation, condition codes,
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| /linux-6.12.1/arch/arm64/kvm/hyp/vhe/ |
| D | Makefile | 12 obj-y += ../vgic-v3-sr.o ../aarch32.o ../vgic-v2-cpuif-proxy.o ../entry.o \
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| /linux-6.12.1/arch/arm64/include/uapi/asm/ |
| D | signal.h | 20 /* Required for AArch32 compatibility. */
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| D | fcntl.h | 21 * Using our own definitions for AArch32 (compat) support.
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| /linux-6.12.1/arch/arm64/ |
| D | Kconfig | 591 This option removes the AES hwcap for aarch32 user-space to
610 When running a compat (AArch32) userspace on an affected Cortex-A53
652 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
661 from AArch32 userspace.
1324 The system will use 16KB pages support. AArch32 emulation
1334 look-up. AArch32 emulation requires applications compiled
1693 kernel at EL1. AArch32-specific components such as system calls,
1698 that you will only be able to execute AArch32 binaries that were compiled
1803 instructions for AArch32 userspace code. When this option is
1814 AArch32 EL0, and is deprecated in ARMv8.
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| /linux-6.12.1/arch/arm64/kvm/ |
| D | sys_regs.c | 42 * For AArch32, we only take care of what is being trapped. Anything
434 * for both AArch64 and AArch32 accesses.
455 if (p->Op0 == 0) { /* AArch32 */ in access_gic_sgi()
1304 /* The LC bit is RES1 when AArch32 is not supported */ in set_pmcr()
1637 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any in aa32_id_visibility()
2337 /* AArch64 mappings of the AArch32 ID registers */
2840 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */
3375 * AArch32 debug register mappings
3377 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
3378 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
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| /linux-6.12.1/crypto/ |
| D | aegis128-neon-inner.c | 178 * AArch32 does not provide these intrinsics natively because it does not
179 * implement the underlying instructions. AArch32 only provides 64-bit
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| /linux-6.12.1/tools/testing/selftests/kvm/aarch64/ |
| D | aarch32_id_regs.c | 7 * Test that KVM handles the AArch64 views of the AArch32 ID registers as RAZ
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