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/linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dphy_shim.h80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
84 /* Index for first 40MHz OFDM SISO rate */
86 /* Index for first 40MHz OFDM CDD rate */
89 /* Index for first 20MHz MCS SISO rate */
91 /* Index for first 20MHz MCS CDD rate */
93 /* Index for first 20MHz MCS STBC rate */
95 /* Index for first 20MHz MCS SDM rate */
97 /* Index for first 40MHz MCS SISO rate */
99 /* Index for first 40MHz MCS CDD rate */
[all …]
Dchannel.c60 #define BRCM_2GHZ_2412_2462 REG_RULE(2412-10, 2462+10, 40, 0, 19, 0)
64 #define BRCM_5GHZ_5180_5240 REG_RULE(5180-10, 5240+10, 40, 0, 21, \
66 #define BRCM_5GHZ_5260_5320 REG_RULE(5260-10, 5320+10, 40, 0, 21, \
69 #define BRCM_5GHZ_5500_5700 REG_RULE(5500-10, 5700+10, 40, 0, 21, \
72 #define BRCM_5GHZ_5745_5825 REG_RULE(5745-10, 5825+10, 40, 0, 21, \
93 /* tx 20 MHz power limits, qdBm units */
95 /* tx 40 MHz power limits, qdBm units */
239 /* 20 MHz Legacy OFDM SISO */ in brcms_c_channel_min_txpower_limits_with_local_constraint()
243 /* 20 MHz Legacy OFDM CDD */ in brcms_c_channel_min_txpower_limits_with_local_constraint()
248 /* 40 MHz Legacy OFDM SISO */ in brcms_c_channel_min_txpower_limits_with_local_constraint()
[all …]
Dchannel.h28 #define BRCMS_NO_40MHZ 0x08 /* Flag for No MIMO 40MHz */
29 #define BRCMS_NO_MIMO 0x10 /* Flag for No MIMO, 20 or 40 MHz */
/linux-6.12.1/drivers/clk/uniphier/
Dclk-uniphier-sys.c36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
[all …]
/linux-6.12.1/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
96 geometry 640 480 640 480 32 timings 23168 104 40 25 1 64 3 endmode
[all …]
/linux-6.12.1/net/wireless/tests/
Dchan.c44 .desc = "identical 20 MHz",
53 .desc = "identical 40 MHz",
62 .desc = "identical 80 MHz",
71 .desc = "identical 160 MHz",
75 .center_freq1 = 5955 + 10 + 20 + 40,
80 .desc = "identical 320 MHz",
84 .center_freq1 = 5955 + 10 + 20 + 40 + 80,
89 .desc = "20 MHz in 320 MHz\n",
98 .center_freq1 = 5955 + 10 + 20 + 40 + 80,
103 .desc = "different 20 MHz",
[all …]
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/
Dmt76x02_dfs.c29 /* 20MHz */
32 RADAR_SPEC(0, 40, 4, 59, 96, 380, 150, 4900, 100096, 40, 0,
38 /* 40MHz */
41 RADAR_SPEC(0, 40, 4, 59, 96, 380, 150, 4900, 100096, 40, 0,
47 /* 80MHz */
50 RADAR_SPEC(0, 40, 4, 59, 96, 380, 150, 4900, 100096, 40, 0,
59 /* 20MHz */
64 RADAR_SPEC(0, 40, 4, 54, 96, 480, 150, 2900, 80100, 40, 0,
68 /* 40MHz */
73 RADAR_SPEC(0, 40, 4, 54, 96, 480, 150, 2900, 80100, 40, 0,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
124 Defines the auto PD disable frequency in MHz.
128 minimum: 1000000 # In case anyone thought this was MHz.
140 default: 40
156 default: 40
164 default: 40
176 minimum: 1000000 # In case anyone thought this was MHz.
204 default: 40
212 default: 40
[all …]
/linux-6.12.1/drivers/gpu/drm/tests/
Ddrm_kunit_edid.h12 * 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
13 * 45 00 40 84 63 00 00 1e 00 00 00 fc 00 54 65 73
41 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
46 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
70 * 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
71 * 45 00 40 84 63 00 00 1e 00 00 00 fc 00 54 65 73
106 * DMT 0x04: 640x480 59.940476 Hz 4:3 31.469 kHz 25.175000 MHz
109 * DTD 1: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz (1600 mm x 900 mm)
114 * Monitor ranges (GTF): 50-70 Hz V, 30-70 kHz H, max dotclock 150 MHz
128 * VIC 16: 1920x1080 60.000000 Hz 16:9 67.500 kHz 148.500000 MHz
[all …]
/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/fw/api/
Dphy-ctxt.h20 /* and 320 MHz for EHT */
27 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
31 * 40Mhz |____|____|
32 * 80Mhz |____|____|____|____|
33 * 160Mhz |____|____|____|____|____|____|____|____|
34 * 320MHz |____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|____|
145 * @sbb_bandwidth: 0 disabled, 1 - 40Mhz ... 4 - 320MHz
Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
121 * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
[all …]
Dmac.h36 * @MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
449 * (0=SISO, 1=MIMO2) x (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz)
461 * Nss (0-siso, 1-mimo2) x BW (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz) x
473 * (0=SISO, 1=MIMO2) x (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz)
486 * BW (0-20MHz, 1-40MHz, 2-80MHz, 3-160MHz, 4-320MHz) x
522 * extended to 20us for BW > 160Mhz or for MCS w/ 4096-QAM.
/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/mvm/tests/
Dlinks.c123 ….desc = "UHB, BSS Load IE (40 percent), active link, chan_load_by_us=50 (invalid) percent. No punc…
133 { .desc = "HB, 80 MHz, no channel load factor, punctured percentage 0",
142 { .desc = "HB, 160 MHz, no channel load factor, punctured percentage 25",
151 { .desc = "UHB, 320 MHz, no channel load factor, punctured percentage 12.5 (2/16)",
160 { .desc = "HB, 160 MHz, channel load 20, channel load by us 10, punctured percentage 25",
281 .desc = "RSSI: LB, 20 MHz, low",
289 .desc = "RSSI: UHB, 20 MHz, high",
298 .desc = "RSSI: UHB, 40 MHz, low",
307 .desc = "RSSI: UHB, 40 MHz, high",
316 .desc = "RSSI: UHB, 80 MHz, low",
[all …]
/linux-6.12.1/drivers/clk/
Dclk-tps68470.c41 * frequency range of 3 MHz to 27 MHz by a programmable
44 * of 4 MHz to 64 MHz in increments of 0.1 MHz.
53 * BOOST should be as close as possible to 2Mhz
56 * BUCK should be as close as possible to 5.2Mhz
60 * 20Mhz 170 32 1 19.2Mhz
61 * 20Mhz 170 40 1 20Mhz
62 * 20Mhz 170 80 1 24Mhz
65 { 20000000, 170, 40, 1, 3, 4 },
/linux-6.12.1/drivers/scsi/
Dqlogicfas408.h28 Please set this for your card. Most Qlogic cards are 40 Mhz. The
29 Control Concepts ISA (not VLB) is 24 Mhz */
31 #define XTALFREQ 40
49 /* This will set fast (10Mhz) synchronous timing when set to 1
72 of the 40Mhz clock. If FASTCLK is 1, specifying 01 (1/2) will
/linux-6.12.1/drivers/media/tuners/
Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
52 25 40 ? chip initialization
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/linux-6.12.1/net/mac80211/tests/
Dtpe.c34 .desc = "identical 20 MHz",
42 .desc = "identical 40 MHz",
50 .desc = "identical 80+80 MHz",
60 .desc = "identical 320 MHz",
68 .desc = "lower 160 MHz of 320 MHz",
76 .desc = "upper 160 MHz of 320 MHz",
84 .desc = "upper 160 MHz of 320 MHz, go to 40",
92 .desc = "secondary 80 above primary in 80+80 MHz",
102 .desc = "secondary 80 below primary in 80+80 MHz",
112 .desc = "secondary 80 below primary in 80+80 MHz, go to 20",
[all …]
/linux-6.12.1/drivers/clk/mvebu/
Darmada-39x.c24 * 0 = 250 MHz
25 * 1 = 200 MHz
28 * 0 = 25 Mhz
29 * 1 = 40 Mhz
113 return 40 * 1000 * 1000; in armada_39x_refclk_ratio()
/linux-6.12.1/drivers/net/wireless/ath/wcn36xx/
Dhal.h150 WCN36XX_HAL_DEL_BA_REQ = 40,
408 /* 20MHz IF bandwidth centered on IF carrier */
411 /* 40MHz IF bandwidth with lower 20MHz supporting the primary channel */
414 /* 40MHz IF bandwidth centered on IF carrier */
417 /* 40MHz IF bandwidth with higher 20MHz supporting the primary ch */
420 /* 20/40MHZ offset LOW 40/80MHZ offset CENTERED */
423 /* 20/40MHZ offset CENTERED 40/80MHZ offset CENTERED */
426 /* 20/40MHZ offset HIGH 40/80MHZ offset CENTERED */
429 /* 20/40MHZ offset LOW 40/80MHZ offset LOW */
432 /* 20/40MHZ offset HIGH 40/80MHZ offset LOW */
[all …]
/linux-6.12.1/drivers/phy/ralink/
Dphy-mt7621-pci.c142 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
147 dev_dbg(dev, "Xtal is 40MHz\n"); in mt7621_set_phy_for_ssc()
148 } else if (clk_rate == 25000000) { /* 25MHz Xal */ in mt7621_set_phy_for_ssc()
174 dev_dbg(dev, "Xtal is 25MHz\n"); in mt7621_set_phy_for_ssc()
175 } else { /* 20MHz Xtal */ in mt7621_set_phy_for_ssc()
179 dev_dbg(dev, "Xtal is 20MHz\n"); in mt7621_set_phy_for_ssc()
199 if (clk_rate == 40000000) { /* 40MHz Xtal */ in mt7621_set_phy_for_ssc()
/linux-6.12.1/drivers/ata/
Dpata_hpt37x.c595 * @freq: Reported frequency in MHz
597 * Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50
598 * and 3 for 66Mhz)
603 if (freq < 40) in hpt37x_clock_slot()
604 return 0; /* 33Mhz slot */ in hpt37x_clock_slot()
606 return 1; /* 40Mhz slot */ in hpt37x_clock_slot()
608 return 2; /* 50Mhz slot */ in hpt37x_clock_slot()
609 return 3; /* 60Mhz slot */ in hpt37x_clock_slot()
688 freq = (fcnt * base) / 192; /* in MHz */ in hpt37x_pci_clock()
691 if (freq < 40) in hpt37x_pci_clock()
[all …]
/linux-6.12.1/drivers/video/fbdev/
Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
53 "mac9", 56, 800, 600, 27778, 112, 40, 22, 1, 72, 2,
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
68 /* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/b43/
Dxmit.h120 #define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
165 #define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
166 #define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
167 #define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
168 #define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
169 #define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
170 #define B43_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */
344 #define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */
/linux-6.12.1/Documentation/scsi/
Daic7xxx.rst26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dmpc5121.dtsi35 timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
36 bus-frequency = <198000000>; /* 198 MHz csb bus */
37 clock-frequency = <396000000>; /* 396 MHz ppc core */
96 bus-frequency = <66000000>; /* 66 MHz ips bus */
352 interrupts = <40 0x8>;
364 interrupts = <40 0x8>;
376 interrupts = <40 0x8>;
388 interrupts = <40 0x8>;
400 interrupts = <40 0x8>;
412 interrupts = <40 0x8>;
[all …]

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