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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddisplay_mode_vba_util_32.c46 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dml32_dscceComputeDelay()
52 // N422/N420 operate at 2 pixels per clock in dml32_dscceComputeDelay()
57 pixelsPerClock = 2; in dml32_dscceComputeDelay()
59 pixelsPerClock = 2; in dml32_dscceComputeDelay()
86 wx = (w + 2) / 3; in dml32_dscceComputeDelay()
90 ax = (a + 2) / 3 + D + 6 + 1; in dml32_dscceComputeDelay()
98 //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels in dml32_dscceComputeDelay()
120 Delay = Delay + 2; in dml32_dscComputeDelay()
126 Delay = Delay + 2; in dml32_dscComputeDelay()
132 Delay = Delay + 2; in dml32_dscComputeDelay()
[all …]
/linux-6.12.1/tools/lib/
Dlist_sort.c14 __attribute__((nonnull(2,3,4)))
50 __attribute__((nonnull(2,3,4,5)))
119 * 2:1 balanced merges. Given two pending sublists of size 2^k, they are
120 * merged to a size-2^(k+1) list as soon as we have 2^k following elements.
122 * Thus, it will avoid cache thrashing as long as 3*2^k elements can
131 * Each time we increment "count", we set one bit (bit k) and clear
132 * bits k-1 .. 0. Each time this happens (except the very first time
133 * for each bit, when count increments to 2^k), we merge two lists of
134 * size 2^k into one list of size 2^(k+1).
137 * 2^k, which is when we have 2^k elements pending in smaller lists,
[all …]
/linux-6.12.1/drivers/ata/pata_parport/
Dfrpw.c30 static int cont_map[2] = { 0x08, 0x10 };
59 int h, l, k, ph; in frpw_read_block_int() local
64 for (k = 0; k < count; k++) { in frpw_read_block_int()
67 buf[k] = j44(l, h); in frpw_read_block_int()
73 ph = 2; in frpw_read_block_int()
76 for (k = 0; k < count; k++) { in frpw_read_block_int()
78 buf[k] = r0(); in frpw_read_block_int()
79 ph = 2 - ph; in frpw_read_block_int()
84 case 2: in frpw_read_block_int()
86 for (k = 0; k < count; k++) in frpw_read_block_int()
[all …]
Dfriq.c44 static int cont_map[2] = { 0x08, 0x10 };
71 int h, l, k, ph; in friq_read_block_int() local
76 for (k = 0; k < count; k++) { in friq_read_block_int()
79 buf[k] = j44(l, h); in friq_read_block_int()
84 ph = 2; in friq_read_block_int()
87 for (k = 0; k < count; k++) { in friq_read_block_int()
89 buf[k] = r0(); in friq_read_block_int()
90 ph = 2 - ph; in friq_read_block_int()
94 case 2: in friq_read_block_int()
96 for (k = 0; k < count - 2; k++) in friq_read_block_int()
[all …]
Depia.c23 * 1 5/3 reads on ports 1 & 2, 8-bit writes
24 * 2 8-bit reads and writes
37 static int cont_map[2] = { 0, 0x80 };
57 case 2: in epia_read_regr()
81 case 2: in epia_write_regr()
129 int k, ph, a, b; in epia_read_block() local
135 for (k = 0; k < count; k++) { in epia_read_block()
136 w2(2+ph); a = r1(); in epia_read_block()
138 buf[k] = j44(a, b); in epia_read_block()
147 for (k = 0; k < count; k++) { in epia_read_block()
[all …]
Dkbic.c33 static int cont_map[2] = { 0x80, 0x40 };
50 case 2: in kbic_read_regr()
72 case 2: in kbic_write_regr()
128 int k, a, b; in kbic_read_block() local
133 for (k = 0; k < count / 2; k++) { in kbic_read_block()
138 buf[2 * k] = j44(a, b); in kbic_read_block()
143 buf[2 * k + 1] = j44(a, b); in kbic_read_block()
149 for (k = 0; k < count / 4; k++) { in kbic_read_block()
153 buf[4 * k] = j53(r12w()); in kbic_read_block()
155 buf[4 * k + 1] = j53(r12w()); in kbic_read_block()
[all …]
Depat.c33 * cont = 2 internal EPAT registers
44 case 2: in epat_write_regr()
71 case 2: in epat_read_regr()
87 int k, ph, a, b; in epat_read_block() local
94 for (k = 0; k < count; k++) { in epat_read_block()
95 if (k == count-1) in epat_read_block()
103 buf[k] = j44(a, b); in epat_read_block()
112 for (k = 0; k < count; k++) { in epat_read_block()
113 if (k == count - 1) in epat_read_block()
117 buf[k] = j53(a, b); in epat_read_block()
[all …]
Don26.c21 * 2 8-bit EPP mode
47 r = (regr << 2) + 1 + cont; in on26_read_regr()
60 case 2: in on26_read_regr()
74 int r = (regr << 2) + 1 + cont; in on26_write_regr()
82 case 2: in on26_write_regr()
113 w0(2); P1; w0(8); P2; in on26_connect()
114 w0(2); P1; w0(x); P2; in on26_connect()
119 if (pi->mode >= 2) { in on26_disconnect()
156 w0(2); P1; w0(0); P2; in on26_test_port()
158 w0(2); P1; w0(8); P2; udelay(100); in on26_test_port()
[all …]
Ddstr.c21 * 2 8-bit EPP mode
37 static int cont_map[2] = { 0x20, 0x40 };
59 case 2: in dstr_read_regr()
74 if (pi->mode >= 2) in dstr_write_regr()
85 case 2: in dstr_write_regr()
117 int k, a, b; in dstr_read_block() local
128 for (k = 0; k < count; k++) { in dstr_read_block()
131 buf[k] = j44(a, b); in dstr_read_block()
136 for (k = 0; k < count; k++) { in dstr_read_block()
138 buf[k] = r0(); in dstr_read_block()
[all …]
Dfit3.c44 case 2: in fit3_write_regr()
70 case 2: in fit3_read_regr()
83 int k, a, b, c, d; in fit3_read_block() local
88 for (k = 0; k < count / 2; k++) { in fit3_read_block()
93 buf[2 * k] = j44(a, b); in fit3_read_block()
94 buf[2 * k + 1] = j44(c, d); in fit3_read_block()
101 for (k = 0; k < count / 2; k++) { in fit3_read_block()
104 buf[2 * k] = a; in fit3_read_block()
105 buf[2 * k + 1] = b; in fit3_read_block()
110 case 2: in fit3_read_block()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_mode_vba_30.c419 unsigned int CursorWidth[][2],
420 unsigned int CursorBPP[][2],
680 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
686 // N422/N420 operate at 2 pixels per clock in dscceComputeDelay()
691 pixelsPerClock = 2; in dscceComputeDelay()
696 pixelsPerClock = 2; in dscceComputeDelay()
722 wx = (w + 2) / 3; in dscceComputeDelay()
726 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
734 //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels in dscceComputeDelay()
745 Delay = Delay + 2; in dscComputeDelay()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_mode_vba_20v2.c319 2)); in adjust_ReturnBW()
336 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
342 // N422/N420 operate at 2 pixels per clock in dscceComputeDelay()
347 pixelsPerClock = 2; in dscceComputeDelay()
374 wx = (w + 2) / 3; in dscceComputeDelay()
378 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
386 //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels in dscceComputeDelay()
397 Delay = Delay + 2; in dscComputeDelay()
403 Delay = Delay + 2; in dscComputeDelay()
409 Delay = Delay + 2; in dscComputeDelay()
[all …]
Ddisplay_mode_vba_20.c295 2)); in adjust_ReturnBW()
312 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
318 // N422/N420 operate at 2 pixels per clock in dscceComputeDelay()
323 pixelsPerClock = 2; in dscceComputeDelay()
350 wx = (w + 2) / 3; in dscceComputeDelay()
354 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
362 //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels in dscceComputeDelay()
373 Delay = Delay + 2; in dscComputeDelay()
379 Delay = Delay + 2; in dscComputeDelay()
385 Delay = Delay + 2; in dscComputeDelay()
[all …]
/linux-6.12.1/lib/
Dlist_sort.c15 __attribute__((nonnull(2,3,4)))
51 __attribute__((nonnull(2,3,4,5)))
130 * 2:1 balanced merges. Given two pending sublists of size 2^k, they are
131 * merged to a size-2^(k+1) list as soon as we have 2^k following elements.
133 * Thus, it will avoid cache thrashing as long as 3*2^k elements can
142 * Each time we increment "count", we set one bit (bit k) and clear
143 * bits k-1 .. 0. Each time this happens (except the very first time
144 * for each bit, when count increments to 2^k), we merge two lists of
145 * size 2^k into one list of size 2^(k+1).
148 * 2^k, which is when we have 2^k elements pending in smaller lists,
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_mode_vba_21.c507 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
513 // N422/N420 operate at 2 pixels per clock in dscceComputeDelay()
518 pixelsPerClock = 2; in dscceComputeDelay()
545 wx = (w + 2) / 3; in dscceComputeDelay()
549 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
557 //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels in dscceComputeDelay()
568 Delay = Delay + 2; in dscComputeDelay()
574 Delay = Delay + 2; in dscComputeDelay()
580 Delay = Delay + 2; in dscComputeDelay()
586 Delay = Delay + 2; in dscComputeDelay()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn314/
Ddisplay_mode_vba_314.c54 // Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
264 unsigned int k,
701 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
707 // N422/N420 operate at 2 pixels per clock in dscceComputeDelay()
711 pixelsPerClock = 2; in dscceComputeDelay()
715 pixelsPerClock = 2; in dscceComputeDelay()
742 wx = (w + 2) / 3; in dscceComputeDelay()
746 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
754 //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels in dscceComputeDelay()
765 Delay = Delay + 2; in dscComputeDelay()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddisplay_mode_vba_31.c56 // Delay in DCFCLK from ARB to DET (1st num is ARB to SDPIF, 2nd number is SDPIF to DET)
255 unsigned int k,
683 …mSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
689 // N422/N420 operate at 2 pixels per clock in dscceComputeDelay()
693 pixelsPerClock = 2; in dscceComputeDelay()
697 pixelsPerClock = 2; in dscceComputeDelay()
724 wx = (w + 2) / 3; in dscceComputeDelay()
728 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
736 //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels in dscceComputeDelay()
747 Delay = Delay + 2; in dscComputeDelay()
[all …]
/linux-6.12.1/arch/sparc/crypto/
Dcamellia_asm.S9 CAMELLIA_F(KEY_BASE + 2, I0, I1, I0) \
36 ld [%o0 + 0x00], %f0 ! i0, k[0]
37 ld [%o0 + 0x04], %f1 ! i1, k[1]
38 ld [%o0 + 0x08], %f2 ! i2, k[2]
39 ld [%o0 + 0x0c], %f3 ! i3, k[3]
40 std %f0, [%o1 + 0x00] ! k[0, 1]
42 std %f2, [%o1 + 0x08] ! k[2, 3]
49 std %f0, [%o1 + 0x20] ! k[8, 9]
57 std %f2, [%o1 + 0x28] ! k[10, 11]
70 CAMELLIA_F(16, 2, 0, 2)
[all …]
/linux-6.12.1/include/uapi/linux/
Dkeyboard.h8 #define KG_CTRL 2
31 #define KT_SPEC 2
45 #define K(t,v) (((t)<<8)|(v)) macro
49 #define K_F1 K(KT_FN,0)
50 #define K_F2 K(KT_FN,1)
51 #define K_F3 K(KT_FN,2)
52 #define K_F4 K(KT_FN,3)
53 #define K_F5 K(KT_FN,4)
54 #define K_F6 K(KT_FN,5)
55 #define K_F7 K(KT_FN,6)
[all …]
/linux-6.12.1/Documentation/admin-guide/media/
Ddvb_intro.rst133 T 177500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
134 T 184500000 7MHz AUTO AUTO QAM64 8k 1/8 NONE
135 T 191625000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
136 T 219500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
137 T 226500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
138 T 557625000 7MHz AUTO AUTO QPSK 8k 1/16 NONE
151 TRANSMISSION_MODE = 8K
179 TRANSMISSION_MODE = 8K
194 TRANSMISSION_MODE = 8K
198 [ABC TV 2]
[all …]
/linux-6.12.1/crypto/
Dserpent_generic.c25 ({ b ^= d; b ^= c; b ^= a; b ^= PHI ^ i; b = rol32(b, 11); k[j] = b; })
28 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
31 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
36 #define K(x0, x1, x2, x3, i) ({ \ macro
37 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
38 x1 ^= k[4*(i)+1]; x0 ^= k[4*(i)+0]; \
48 x0 ^= x3; x2 ^= x4; x3 ^= k[4*i+3]; \
49 x1 ^= k[4*i+1]; x0 = rol32(x0, 5); x2 = rol32(x2, 22);\
50 x0 ^= k[4*i+0]; x2 ^= k[4*i+2]; \
54 x0 ^= k[4*i+0]; x1 ^= k[4*i+1]; x2 ^= k[4*i+2]; \
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
Ddml2_core_shared.c764 unsigned int k, m, n; in dml2_core_shared_mode_support() local
804 for (k = 0; k < mode_lib->ms.num_active_planes; k++) in dml2_core_shared_mode_support()
805 …::%s: plane_%d: reserved_vblank_time_ns = %u\n", __func__, k, display_cfg->plane_descriptors[k].ov… in dml2_core_shared_mode_support()
835 for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) { in dml2_core_shared_mode_support()
836 if (display_cfg->plane_descriptors[k].composition.scaler_info.enabled == false in dml2_core_shared_mode_support()
837 && (dml2_core_shared_is_420(display_cfg->plane_descriptors[k].pixel_format) in dml2_core_shared_mode_support()
838 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio != 1.0 in dml2_core_shared_mode_support()
839 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_taps != 1.0 in dml2_core_shared_mode_support()
840 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio != 1.0 in dml2_core_shared_mode_support()
841 || display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps != 1.0)) { in dml2_core_shared_mode_support()
[all …]
/linux-6.12.1/tools/testing/selftests/bpf/progs/
Dtest_jhash.h39 const unsigned char *k = key; in jhash() local
44 a += *(volatile u32 *)(k); in jhash()
45 b += *(volatile u32 *)(k + 4); in jhash()
46 c += *(volatile u32 *)(k + 8); in jhash()
49 k += 12; in jhash()
52 case 12: c += (u32)k[11]<<24; in jhash()
53 case 11: c += (u32)k[10]<<16; in jhash()
54 case 10: c += (u32)k[9]<<8; in jhash()
55 case 9: c += k[8]; in jhash()
56 case 8: b += (u32)k[7]<<24; in jhash()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
Ddisplay_mode_core.c851 …numSlices = number of slices in the horiziontal direction per DSC engine in the set of {1, 2, 3, 4} in dscceComputeDelay()
857 // N422/N420 operate at 2 pixels per clock in dscceComputeDelay()
862 pixelsPerClock = 2; in dscceComputeDelay()
867 pixelsPerClock = 2; in dscceComputeDelay()
893 wx = (w + 2) / 3; in dscceComputeDelay()
897 ax = (a + 2) / 3 + D + 6 + 1; in dscceComputeDelay()
905 //dsc processes 3 pixel containers per cycle and a container can contain 1 or 2 pixels in dscceComputeDelay()
926 Delay = Delay + 2; in dscComputeDelay()
932 Delay = Delay + 2; in dscComputeDelay()
938 Delay = Delay + 2; in dscComputeDelay()
[all …]
/linux-6.12.1/tools/testing/selftests/tc-testing/tc-tests/actions/
Dpolice.json20 "cmdUnderTest": "$TC actions add action police rate 1kbit burst 10k index 1",
46 "$TC actions add action police rate 4Mbit burst 120k index 9"
48 "cmdUnderTest": "$TC actions add action police rate 8kbit burst 24k index 9",
75 "cmdUnderTest": "$TC actions add action police rate 90kbit burst 10k mtu 1k index 98",
102 …"cmdUnderTest": "$TC actions add action police rate 90kbit burst 10k mtu 2kb peakrate 100kbit inde…
105 …"matchPattern": "action order [0-9]*: police 0x3 rate 90Kbit burst 10Kb mtu 2Kb peakrate 100Kbit",
156 "cmdUnderTest": "$TC actions add action police rate 1mbit burst 100k overhead 64 index 64",
159 …"matchPattern": "action order [0-9]*: police 0x40 rate 1Mbit burst 100Kb mtu 2Kb action reclassif…
183 … "cmdUnderTest": "$TC actions add action police rate 2mbit burst 200k linklayer ethernet index 8",
186 …"matchPattern": "action order [0-9]*: police 0x8 rate 2Mbit burst 200Kb mtu 2Kb action reclassify…
[all …]

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