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/linux-6.12.1/crypto/
Dserpent_generic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 ({ b ^= d; b ^= c; b ^= a; b ^= PHI ^ i; b = rol32(b, 11); k[j] = b; })
28 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
31 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
36 #define K(x0, x1, x2, x3, i) ({ \ macro
37 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
38 x1 ^= k[4*(i)+1]; x0 ^= k[4*(i)+0]; \
48 x0 ^= x3; x2 ^= x4; x3 ^= k[4*i+3]; \
49 x1 ^= k[4*i+1]; x0 = rol32(x0, 5); x2 = rol32(x2, 22);\
50 x0 ^= k[4*i+0]; x2 ^= k[4*i+2]; \
[all …]
Dsm3.c1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * SM3 secure hash, as specified by OSCCA GM/T 0004-2012 SM3 and described
4 * at https://datatracker.ietf.org/doc/html/draft-sca-cfrg-sm3-02
7 * Copyright (C) 2017 Gilad Ben-Yossef <gilad@benyossef.com>
15 static const u32 ____cacheline_aligned K[64] = { variable
35 * Transform the message X which consists of 16 32-bit-words. See
36 * GM/T 004-2012 for details.
67 ^ W[(i-9) & 0x0f] \
68 ^ rol32(W[(i-3) & 0x0f], 15)) \
69 ^ rol32(W[(i-13) & 0x0f], 7) \
[all …]
/linux-6.12.1/tools/testing/selftests/bpf/progs/
Dfentry_many_args.c1 // SPDX-License-Identifier: GPL-2.0
15 e == (void *)20 && f == 21 && g == 22; in BPF_PROG()
22 int g, unsigned int h, long i, __u64 j, unsigned long k) in BPF_PROG() argument
25 e == (void *)20 && f == 21 && g == 22 && h == 23 && in BPF_PROG()
26 i == 24 && j == 25 && k == 26; in BPF_PROG()
33 __u64 g, __u64 h, __u64 i, __u64 j, __u64 k) in BPF_PROG() argument
36 e == 20 && f == 21 && g == 22 && h == 23 && in BPF_PROG()
37 i == 24 && j == 25 && k == 26; in BPF_PROG()
Dfexit_many_args.c1 // SPDX-License-Identifier: GPL-2.0
15 e == (void *)20 && f == 21 && g == 22 && ret == 133; in BPF_PROG()
22 int g, unsigned int h, long i, __u64 j, unsigned long k, in BPF_PROG() argument
26 e == (void *)20 && f == 21 && g == 22 && h == 23 && in BPF_PROG()
27 i == 24 && j == 25 && k == 26 && ret == 231; in BPF_PROG()
34 __u64 g, __u64 h, __u64 i, __u64 j, __u64 k, __u64 ret) in BPF_PROG() argument
37 e == 20 && f == 21 && g == 22 && h == 23 && in BPF_PROG()
38 i == 24 && j == 25 && k == 26 && ret == 231; in BPF_PROG()
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Dmd5-asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-offsets.h>
9 #include <asm/asm-compat.h>
40 PPC_STLU r1,-INT_FRAME_SIZE(r1); \
68 addi w0,w0,k0l; /* 1: wk = w + k */ \
70 addis w0,w0,k0h; /* 1: wk = w + k' */ \
71 addis w1,w1,k1h; /* 2: wk = w + k */ \
73 addi w1,w1,k1l; /* 2: wk = w + k' */ \
88 addi w0,w0,k0l; /* 1: wk = w + k */ \
90 addis w0,w0,k0h; /* 1: wk = w + k' */ \
[all …]
Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
49 # poly1305_p10le_4blocks( uint8_t *k, uint32_t mlen, uint8_t *m)
50 # k = 32 bytes key
51 # r3 = k (r, s)
[all …]
/linux-6.12.1/arch/powerpc/lib/
Dtest_emulate_step.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <asm/ppc-opcode.h>
14 #include <asm/code-patching.h>
64 regs->msr = msr; in init_pt_regs()
68 asm volatile("mfmsr %0" : "=r"(regs->msr)); in init_pt_regs()
70 regs->msr |= MSR_FP; in init_pt_regs()
71 regs->msr |= MSR_VEC; in init_pt_regs()
72 regs->msr |= MSR_VSX; in init_pt_regs()
74 msr = regs->msr; in init_pt_regs()
80 pr_info("%-14s : %s\n", mnemonic, result); in show_result()
[all …]
/linux-6.12.1/arch/arc/include/asm/
Dpgtable-levels.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * -------------------------------------------------------
20 * | | <---------- PGDIR_SHIFT ----------> |
21 * | | | <-- PAGE_SHIFT --> |
22 * -------------------------------------------------------
24 * | | --> off in page frame
25 * | ---> index into Page Table
26 * ----> index into Page Directory
36 #define PGDIR_SHIFT 21
40 * Default value provides 11:8:13 (8K), 10:10:12 (4K)
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/linux-6.12.1/include/uapi/linux/
Dkeyboard.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
45 #define K(t,v) (((t)<<8)|(v)) macro
49 #define K_F1 K(KT_FN,0)
50 #define K_F2 K(KT_FN,1)
51 #define K_F3 K(KT_FN,2)
52 #define K_F4 K(KT_FN,3)
53 #define K_F5 K(KT_FN,4)
54 #define K_F6 K(KT_FN,5)
55 #define K_F7 K(KT_FN,6)
56 #define K_F8 K(KT_FN,7)
[all …]
/linux-6.12.1/drivers/clk/berlin/
Dbg2q.c1 // SPDX-License-Identifier: GPL-2.0
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/berlin2q.h>
19 #include "berlin2-div.h"
20 #include "berlin2-pll.h"
130 BERLIN2_DIV_SELECT(REG_CLKSELECT0, 21),
176 BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21),
205 BERLIN2_DIV_SELECT(REG_CLKSELECT1, 21),
218 BERLIN2_DIV_GATE(REG_CLKENABLE, 21),
[all …]
/linux-6.12.1/arch/arm64/include/asm/
Dkvm_arm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
53 #define HCR_TACR (UL(1) << 21)
127 #define VTCR_EL2_HA (1 << 21)
150 * We configure the Stage-2 page tables to always restrict the IPA space to be
156 * Note that when using 4K pages, we concatenate two first level page tables
157 * together. With 16K pages, we concatenate 16 first level page tables.
169 * -----------------------------------------
170 * | Entry level | 4K | 16K/64K |
171 * ------------------------------------------
[all …]
/linux-6.12.1/Documentation/translations/zh_CN/core-api/
Dcpu_hotplug.rst1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/core-api/cpu_hotplug.rst
79 hot-add/hot-remove。目前还没有定死规定。典型的用法是在启动时启动拓扑结构，这时
95 $ ls -lh /sys/devices/system/cpu
97 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu0
98 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu1
99 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu2
100 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu3
101 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu4
102 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu5
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dmarvell,armada-380-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/marvell,armada-380-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RTC controller for the Armada 38x, 7K and 8K SoCs
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
13 - $ref: rtc.yaml#
18 - marvell,armada-380-rtc
19 - marvell,armada-8k-rtc
23 - description: RTC base address size
[all …]
/linux-6.12.1/arch/powerpc/include/asm/nohash/32/
Dmmu-8xx.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * During software tablewalk, the registers used perform mask/shift-add
32 * into bit 21 in the ITLBmiss handler (bit 21 is the middle bit), which means
43 * 4-15 => Not Used
66 #define MI_PS512K 0x00000004 /* 512K page size */
67 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
76 #define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
91 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
141 #define MD_PS512K 0x00000004 /* 512K page size */
142 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
[all …]
/linux-6.12.1/arch/powerpc/platforms/pasemi/
Diommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2008, PA Semi, Inc
23 #define IOBMAP_PAGE_MASK (IOBMAP_PAGE_SIZE - 1)
51 /* Base of the 64 4-byte L1 registers */
88 bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT; in iobmap_build()
90 ip = ((u32 *)tbl->it_base) + index; in iobmap_build()
92 while (npages--) { in iobmap_build()
114 bus_addr = (tbl->it_offset + index) << IOBMAP_PAGE_SHIFT; in iobmap_free()
116 ip = ((u32 *)tbl->it_base) + index; in iobmap_free()
118 while (npages--) { in iobmap_free()
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dvlv_dpio_phy_regs.h1 /* SPDX-License-Identifier: MIT */
12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
29 #define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */
30 #define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */
34 #define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k)) argument
35 #define DPIO_P1_DIV_MASK REG_GENMASK(23, 21)
85 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21)
95 #define DPIO_PCS_USEDCLKCHANNEL REG_BIT(21)
[all …]
/linux-6.12.1/include/linux/
Dplist.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Descending-priority-sorted double-linked list
5 * (C) 2002-2003 Intel Corp
6 * Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>.
8 * 2001-2005 (c) MontaVista Software, Inc.
14 * Oleg Nesterov <oleg@tv-sign.ru>
18 * This is a priority-sorted list of nodes; each node has a
21 * Addition is O(K), removal is O(1), change of priority of a node is
22 * O(K) and K is the number of RT priority levels used in the system.
23 * (1 <= K <= 99)
[all …]
/linux-6.12.1/arch/arm64/crypto/
Dsm3-neon-core.S1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sm3-neon-core.S - SM3 secure hash using NEON instructions
92 ror o, a, #(32 - n);
121 #define R(i, a, b, c, d, e, f, g, h, k, K_LOAD, round, widx, wtype, IOP, iop_param) \ argument
128 add k, k, e; \
133 add k, k, t0; \
137 rolw(k, k, 7); /* rol (t0 + e + t), 7) => k */ \
139 add h, h, k; /* h + w1 + k => h */ \
142 eor t0, t0, k; /* k ^ t0 => t0 */ \
148 eor h, t3, t3, ror #(32-9); \
[all …]
/linux-6.12.1/drivers/gpu/drm/
Ddrm_panic_qr.rs1 // SPDX-License-Identifier: MIT
25 //! * <https://github.com/kennytm/qrcode-rust>
36 const P7: [u8; 7] = [87, 229, 146, 149, 238, 102, 21];
53 232, 87, 96, 227, 21,
56 173, 125, 158, 2, 103, 182, 118, 17, 145, 201, 111, 28, 165, 53, 161, 21, 245, 142, 13, 102,
60 168, 223, 200, 104, 224, 234, 108, 180, 110, 190, 195, 147, 205, 27, 232, 201, 21, 43, 245, 87,
69 /// - Error Correction polynomial.
70 /// - Number of blocks in group 1.
71 /// - Number of blocks in group 2.
72 /// - Block size in group 1.
[all …]
/linux-6.12.1/Documentation/networking/device_drivers/ethernet/chelsio/
Dcxgb.rst1 .. SPDX-License-Identifier: GPL-2.0
35 Adaptive Interrupts (adaptive-rx)
36 ---------------------------------
46 By default, adaptive-rx is disabled.
47 To enable adaptive-rx::
49 ethtool -C <interface> adaptive-rx on
51 To disable adaptive-rx, use ethtool::
53 ethtool -C <interface> adaptive-rx off
55 After disabling adaptive-rx, the timer latency value will be set to 50us.
56 You may set the timer latency after disabling adaptive-rx::
[all …]
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
51 if (IS_VENDOR_8812A_C_CUT(rtlhal->version)) { in rtl8812ae_fixspur()
78 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { in rtl8812ae_fixspur()
146 spin_lock(&rtlpriv->locks.rf_lock); in rtl8821ae_phy_query_rf_reg()
152 spin_unlock(&rtlpriv->locks.rf_lock); in rtl8821ae_phy_query_rf_reg()
172 spin_lock(&rtlpriv->locks.rf_lock); in rtl8821ae_phy_set_rf_reg()
183 spin_unlock(&rtlpriv->locks.rf_lock); in rtl8821ae_phy_set_rf_reg()
207 !((rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) || in _rtl8821ae_phy_rf_serial_read()
208 (IS_VENDOR_8812A_C_CUT(rtlhal->version)))) in _rtl8821ae_phy_rf_serial_read()
[all …]
/linux-6.12.1/drivers/mtd/nand/raw/
Dnand_onfi.c1 // SPDX-License-Identifier: GPL-2.0
4 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
10 * rework for 2K page size chips
24 while (len--) { in onfi_crc16()
37 struct nand_device *base = &chip->base; in nand_flash_detect_ext_param_page()
47 len = le16_to_cpu(p->ext_param_page_length) * 16; in nand_flash_detect_ext_param_page()
50 return -ENOMEM; in nand_flash_detect_ext_param_page()
57 sizeof(*p) * p->num_of_param_pages, in nand_flash_detect_ext_param_page()
62 ret = -EINVAL; in nand_flash_detect_ext_param_page()
63 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) in nand_flash_detect_ext_param_page()
[all …]
/linux-6.12.1/include/dt-bindings/clock/
Dtegra20-car.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This header provides constants for binding nvidia,tegra20-car.
41 #define TEGRA20_CLK_GR2D 21
111 #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
128 #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
153 #define TEGRA20_CLK_COP 129 /* a/k/a avp */
154 #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
/linux-6.12.1/include/media/
Dtuner.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * tuner.h - definition for different tuners
5 * Copyright (C) 1997 Markus Schroeder (schroedm@uni-duesseldorf.de)
6 * minor modifications by Ralph Metzler (rjkm@thp.uni-koeln.de)
14 #include <media/v4l2-mc.h>
41 #define TUNER_TEMIC_4006FN5_MULTI_PAL 19 /* B/G, I and D/K autodetected (3X 7595, 7606, 7657) */
44 #define TUNER_TEMIC_4039FR5_NTSC 21 /* incl. FM radio (3X 7246, 7578, 7732) */
45 #define TUNER_TEMIC_4046FM5 22 /* you must actively select B/G, D/K, I, L, L` ! (3X 7804, 7806, 8…
48 #define TUNER_PHILIPS_FQ1216ME 24 /* you must actively select B/G/D/K, I, L, L` */
55 #define TUNER_TEMIC_4009FN5_MULTI_PAL_FM 30 /* B/G, I and D/K autodetected (3X 8155, 8160, 8163) */
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