Lines Matching +full:21 +full:- +full:k
1 // SPDX-License-Identifier: GPL-2.0
5 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
10 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/berlin2q.h>
19 #include "berlin2-div.h"
20 #include "berlin2-pll.h"
130 BERLIN2_DIV_SELECT(REG_CLKSELECT0, 21),
176 BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21),
205 BERLIN2_DIV_SELECT(REG_CLKSELECT1, 21),
218 BERLIN2_DIV_GATE(REG_CLKENABLE, 21),
293 clk_data->num = MAX_CLKS; in berlin2q_clock_setup()
294 hws = clk_data->hws; in berlin2q_clock_setup()
340 int k; in berlin2q_clock_setup() local
342 for (k = 0; k < dd->num_parents; k++) in berlin2q_clock_setup()
343 parent_names[k] = clk_names[dd->parent_ids[k]]; in berlin2q_clock_setup()
345 hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase, in berlin2q_clock_setup()
346 dd->name, dd->div_flags, parent_names, in berlin2q_clock_setup()
347 dd->num_parents, dd->flags, &lock); in berlin2q_clock_setup()
354 hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name, in berlin2q_clock_setup()
355 gd->parent_name, gd->flags, gbase + REG_CLKENABLE, in berlin2q_clock_setup()
356 gd->bit_idx, 0, &lock); in berlin2q_clock_setup()
376 /* register clk-provider */ in berlin2q_clock_setup()
385 CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",