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/linux-6.12.1/drivers/staging/media/ipu3/
Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
18 .sample_patrn_length = 2,
24 .even = { { 0, 3, 122, 7, 3, 0, 0 },
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
[all …]
/linux-6.12.1/drivers/pinctrl/sunplus/
Dsppctl_sp7021.c1 // SPDX-License-Identifier: GPL-2.0
18 D_PIS(0, 0), D_PIS(0, 1), D_PIS(0, 2), D_PIS(0, 3),
19 D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7),
20 D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3),
21 D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7),
22 D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3),
23 D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7),
24 D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3),
25 D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7),
26 D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3),
[all …]
/linux-6.12.1/arch/sh/include/mach-common/mach/
Dsh2007.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define BUS_SZ16 2
15 #define PCMCIA_IO8 2
20 #define PCMCIA_ATTR16 7
25 /* write-read/write-write delay (0-7:0,1,2,3,4,5,6,7) */
28 /* different area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
29 #define IWRWD5 2
30 #define IWRWD6 2
31 /* same area, read-write delay (0-7:0,1,2,3,4,5,6,7) */
32 #define IWRWS5 2
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
43 { 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
45 { 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
47 { 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
49 { 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1,
51 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1,
53 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
54 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
55 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
56 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
[all …]
/linux-6.12.1/Documentation/userspace-api/media/v4l/
Dpixfmt-rgb.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
45 - 'r', 'g' and 'b' denote bits of the red, green and blue components
54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
57 for each component. For instance, the RGB565 format stores a pixel in a 16-bit
[all …]
Dpixfmt-srggb10-ipu3.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-pix-fmt-ipu3-sbggr10:
4 .. _v4l2-pix-fmt-ipu3-sgbrg10:
5 .. _v4l2-pix-fmt-ipu3-sgrbg10:
6 .. _v4l2-pix-fmt-ipu3-srggb10:
13 10-bit Bayer formats
24 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
36 .. flat-table::
38 * - start + 0:
39 - B\ :sub:`0000low`
[all …]
Dpixfmt-packed-yuv.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
30 seen in a 16-bit word, which is then stored in memory in little endian byte
32 format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
33 Cb\ :sub:`5-0` Cr\ :sub:`4-0`], and stored in memory in two bytes,
34 [Cb\ :sub:`2-0` Cr\ :sub:`4-0`] followed by [Y'\ :sub:`4-0` Cb\ :sub:`5-3`].
40 \setlength{\tabcolsep}{2pt}
44 .. flat-table:: Packed YUV 4:4:4 Image Formats (less than 8bpc)
[all …]
Dsubdev-formats.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
17 :widths: 1 1 2
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
[all …]
/linux-6.12.1/drivers/video/fbdev/via/
Dhw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
33 #define VIA_STATE_SUSPEND 2
43 #define IGA2_HOR_TOTAL_SHADOW_FORMULA(x) ((x/8)-5)
44 #define IGA2_HOR_BLANK_END_SHADOW_FORMULA(x, y) (((x+y)/8)-1)
45 #define IGA2_VER_TOTAL_SHADOW_FORMULA(x) ((x)-2)
46 #define IGA2_VER_ADDR_SHADOW_FORMULA(x) ((x)-1)
47 #define IGA2_VER_BLANK_START_SHADOW_FORMULA(x) ((x)-1)
48 #define IGA2_VER_BLANK_END_SHADOW_FORMULA(x, y) ((x+y)-1)
[all …]
/linux-6.12.1/drivers/gpu/drm/display/
Ddrm_dsc_helper.c1 // SPDX-License-Identifier: MIT
35 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header
49 pps_header->HB1 = DP_SDP_PPS; in drm_dsc_dp_pps_header_init()
50 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; in drm_dsc_dp_pps_header_init()
55 * drm_dsc_dp_rc_buffer_size - get rc buffer size in bytes
57 * @rc_buffer_size: number of blocks - 1, according to DPCD offset 63h
82 * drm_dsc_pps_payload_pack() - Populates the DSC PPS
110 pps_payload->dsc_version = in drm_dsc_pps_payload_pack()
111 dsc_cfg->dsc_version_minor | in drm_dsc_pps_payload_pack()
112 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; in drm_dsc_pps_payload_pack()
[all …]
/linux-6.12.1/arch/arm64/include/asm/
Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
21 * C5.2, version:ARM DDI 0487A.f)
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/meteorlake/
Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
25 "Counter": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
54 "Counter": "0,1,2,3,4,5,6,7",
64 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
84 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.12.1/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
9 Version 2 (EeePC) hardware support based on patches
16 2. Extra knobs
22 5. Hardware version 2
25 5.2.1 Parity checking and packet re-synchronization
26 5.2.2 One/Three finger touch
32 6.2.2 Two finger touch
33 7. Hardware version 4
37 7.2.2 Head packet
50 hardware versions unimaginatively called version 1,version 2, version 3
[all …]
/linux-6.12.1/arch/m68k/fpsp040/
Dtbldo.S10 | index with a 10-bit index, with the first
11 | 7 bits the opcode, and the remaining 3
23 |TBLDO idnt 2,1 | Motorola 040 Floating Point Software Package
46 | instruction ;opcode-stag Notes
49 .long smovcr |$00-0 fmovecr all
50 .long smovcr |$00-1 fmovecr all
51 .long smovcr |$00-2 fmovecr all
52 .long smovcr |$00-3 fmovecr all
53 .long smovcr |$00-4 fmovecr all
54 .long smovcr |$00-5 fmovecr all
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/graniterapids/
Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
14 "Counter": "0,1,2,3,4,5,6,7",
23 "Counter": "0,1,2,3,4,5,6,7",
32 "Counter": "0,1,2,3,4,5,6,7",
41 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
81 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/emeraldrapids/
Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
81 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/sapphirerapids/
Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
24 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
62 "Counter": "0,1,2,3,4,5,6,7",
71 "Counter": "0,1,2,3,4,5,6,7",
81 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mtk-mt6397.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include "pinctrl-mtk-common.h"
22 MTK_PIN(PINCTRL_PIN(2, "SRCLKEN_PERI"),
54 MTK_PIN(PINCTRL_PIN(7, "SPI_MOSI"),
72 MTK_FUNCTION(7, "TEST_OUT0")
80 MTK_FUNCTION(7, "TEST_OUT1")
88 MTK_FUNCTION(7, "TEST_OUT2")
92 MTK_EINT_FUNCTION(2, 10),
95 MTK_FUNCTION(2, "EINT10_1X"),
98 MTK_FUNCTION(7, "TEST_OUT3")
[all …]
Dpinctrl-mt6765.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-mtk-mt6765.h"
11 #include "pinctrl-paris.h"
14 * iocfg[0]:0x10005000, iocfg[1]:0x10002C00, iocfg[2]:0x10002800,
16 * iocfg[6]:0x10002500, iocfg[7]:0x10002600.
45 PINS_FIELD_BASE(0, 3, 2, 0x00b0, 0x10, 4, 1),
46 PINS_FIELD_BASE(4, 7, 2, 0x00b0, 0x10, 5, 1),
48 PINS_FIELD_BASE(9, 11, 2, 0x00b0, 0x10, 6, 1),
53 PINS_FIELD_BASE(25, 28, 6, 0x00b0, 0x10, 7, 1),
56 PINS_FIELD_BASE(31, 34, 6, 0x00b0, 0x10, 2, 1),
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/sierraforest/
Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
78 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/grandridge/
Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
13 "Counter": "0,1,2,3,4,5,6,7",
21 "Counter": "0,1,2,3,4,5,6,7",
29 "Counter": "0,1,2,3,4,5,6,7",
37 "Counter": "0,1,2,3,4,5,6,7",
45 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7",
61 "Counter": "0,1,2,3,4,5,6,7",
70 "Counter": "0,1,2,3,4,5,6,7",
78 "Counter": "0,1,2,3,4,5,6,7",
[all …]
/linux-6.12.1/Documentation/translations/zh_CN/core-api/
Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
54 以下示例介绍了打包u64字段的内存布局。打包缓冲区中的字节偏移量始终默认为0，1...7。
62 7 6 5 4
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
[all …]
/linux-6.12.1/drivers/gpu/drm/omapdrm/dss/
Dhdmi5_core.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
28 void __iomem *base = core->base; in hdmi5_core_ddc_init()
54 (v >> 8) & 0xff, 7, 0); in hdmi5_core_ddc_init()
56 v & 0xff, 7, 0); in hdmi5_core_ddc_init()
61 (v >> 8) & 0xff, 7, 0); in hdmi5_core_ddc_init()
63 v & 0xff, 7, 0); in hdmi5_core_ddc_init()
68 (v >> 8) & 0xff, 7, 0); in hdmi5_core_ddc_init()
70 v & 0xff, 7, 0); in hdmi5_core_ddc_init()
75 (v >> 8) & 0xff, 7, 0); in hdmi5_core_ddc_init()
[all …]
/linux-6.12.1/include/linux/mfd/da9062/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2015-2017 Dialog Semiconductor
159 #define DA9062AA_REVERT_SHIFT 7
160 #define DA9062AA_REVERT_MASK BIT(7)
165 #define DA9062AA_DVC_BUSY_SHIFT 2
166 #define DA9062AA_DVC_BUSY_MASK BIT(2)
173 #define DA9062AA_GPI2_SHIFT 2
174 #define DA9062AA_GPI2_MASK BIT(2)
185 #define DA9062AA_LDO3_ILIM_SHIFT 2
186 #define DA9062AA_LDO3_ILIM_MASK BIT(2)
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8173-pinfunc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <dt-bindings/pinctrl/mt65xx.h>
14 #define MT8173_PIN_0_EINT0__FUNC_I2S1_WS (MTK_PIN_NO(0) | 2)
17 #define MT8173_PIN_0_EINT0__FUNC_DBG_MON_A_20_ (MTK_PIN_NO(0) | 7)
21 #define MT8173_PIN_1_EINT1__FUNC_I2S1_BCK (MTK_PIN_NO(1) | 2)
24 #define MT8173_PIN_1_EINT1__FUNC_DBG_MON_A_21_ (MTK_PIN_NO(1) | 7)
26 #define MT8173_PIN_2_EINT2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
27 #define MT8173_PIN_2_EINT2__FUNC_IRDA_TXD (MTK_PIN_NO(2) | 1)
28 #define MT8173_PIN_2_EINT2__FUNC_I2S1_MCK (MTK_PIN_NO(2) | 2)
29 #define MT8173_PIN_2_EINT2__FUNC_SCL5 (MTK_PIN_NO(2) | 3)
[all …]

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