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/linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/
Dmcs_reg.h14 #define MCSX_MCS_TOP_SLAVE_PORT_RESET(a) ({ \ argument
18 if (mcs->hw->mcs_blks > 1) \
20 offset += (a) * 0x8ull; \
24 #define MCSX_MCS_TOP_SLAVE_CHANNEL_CFG(a) ({ \ argument
28 if (mcs->hw->mcs_blks > 1) \
30 offset += (a) * 0x8ull; \
37 if (mcs->hw->mcs_blks > 1) \
41 #define MCSX_MIL_RX_LMACX_CFG(a) ({ \ argument
45 if (mcs->hw->mcs_blks > 1) \
47 offset += (a) * 0x800ull; \
[all …]
/linux-6.12.1/tools/testing/selftests/net/
Dfcnal-test.sh8 # 1. icmp, tcp, udp and netfilter
16 # ns-A | ns-B
23 # ns-A:
24 # eth1: 172.16.1.1/24, 2001:db8:1::1/64
25 # lo: 127.0.0.1/8, ::1/128
26 # 172.16.2.1/32, 2001:db8:2::1/128
27 # red: 127.0.0.1/8, ::1/128
28 # 172.16.3.1/32, 2001:db8:3::1/128
31 # eth1: 172.16.1.2/24, 2001:db8:1::2/64
32 # lo2: 127.0.0.1/8, ::1/128
[all …]
/linux-6.12.1/tools/testing/selftests/drivers/net/mlxsw/
Ddevlink_trap_control.sh12 # | | 2001:db8:1::1/64 |
15 # | | default via 2001:db8:1::2 |
22 # | 2001:db8:1::2/64 |
34 # | | 2001:db8:2::1/64 |
95 simple_if_init $h1 192.0.2.1/24 2001:db8:1::1/64
98 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2
103 ip -6 route del default vrf v$h1 nexthop via 2001:db8:1::2
106 simple_if_fini $h1 192.0.2.1/24 2001:db8:1::1/64
111 simple_if_init $h2 198.51.100.1/24 2001:db8:2::1/64
122 simple_if_fini $h2 198.51.100.1/24 2001:db8:2::1/64
[all …]
/linux-6.12.1/lib/
Dglobtest.c10 /* Boot with "glob.verbose=1" to show successful tests, too */
24 /* Can't get string literals into a particular section, so... */ in test()
47 * pointed-to strings to be in a particular section.
49 * Anyway, a test consists of:
50 * 1. Expected glob_match result: '1' or '0'.
54 * The list of tests is terminated with a final '\0' instead of
55 * a glob_match result character.
59 "1" "a\0" "a\0"
60 "0" "a\0" "b\0"
61 "0" "a\0" "aa\0"
[all …]
/linux-6.12.1/kernel/bpf/
Dtnum.c4 * A tnum tracks knowledge about the bits of a value. Each bit can be either
5 * known (0 or 1), or unknown (x). Arithmetic operations on tnums will
13 /* A completely unknown value */
14 const struct tnum tnum_unknown = { .value = 0, .mask = -1 };
26 /* special case, needed because 1ULL << 64 is undefined */ in tnum_range()
29 /* e.g. if chi = 4, bits = 3, delta = (1<<3) - 1 = 7. in tnum_range()
30 * if chi = 0, bits = 0, delta = (1<<0) - 1 = 0, so we return in tnum_range()
33 delta = (1ULL << bits) - 1; in tnum_range()
37 struct tnum tnum_lshift(struct tnum a, u8 shift) in tnum_lshift() argument
39 return TNUM(a.value << shift, a.mask << shift); in tnum_lshift()
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/ivytown/
Duncore-power.json4 "Counter": "0,1,2,3",
6 "PerPkg": "1",
7 …a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was…
12 "Counter": "0,1,2,3",
15 "PerPkg": "1",
21 "Counter": "0,1,2,3",
24 "PerPkg": "1",
30 "Counter": "0,1,2,3",
33 "PerPkg": "1",
39 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/arch/powerpc/crypto/
Dmd5-asm.S61 #define R_00_15(a, b, c, d, w0, w1, p, q, off, k0h, k0l, k1h, k1l) \ argument
63 and rT0,b,c; /* 1: f = b and c */ \
65 andc rT1,d,b; /* 1: f' = ~b and d */ \
67 or rT0,rT0,rT1; /* 1: f = f or f' */ \
68 addi w0,w0,k0l; /* 1: wk = w + k */ \
69 add a,a,rT0; /* 1: a = a + f */ \
70 addis w0,w0,k0h; /* 1: wk = w + k' */ \
72 add a,a,w0; /* 1: a = a + wk */ \
74 rotrwi a,a,p; /* 1: a = a rotl x */ \
75 add d,d,w1; /* 2: a = a + wk */ \
[all …]
/linux-6.12.1/tools/testing/selftests/net/forwarding/
Dtc_flower.sh44 tc filter add dev $h2 ingress protocol ip pref 1 handle 101 flower \
49 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac -A 192.0.2.1 -B 192.0.2.2 \
52 tc_check_packets "dev $h2 ingress" 101 1
53 check_fail $? "Matched on a wrong filter"
58 tc filter del dev $h2 ingress protocol ip pref 1 handle 101 flower
70 tc filter add dev $h2 ingress protocol ip pref 1 handle 101 flower \
75 $MZ $h1 -c 1 -p 64 -a $h1mac -b $h2mac -A 192.0.2.1 -B 192.0.2.2 \
78 tc_check_packets "dev $h2 ingress" 101 1
79 check_fail $? "Matched on a wrong filter"
84 tc filter del dev $h2 ingress protocol ip pref 1 handle 101 flower
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/skylake/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 …blicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G)…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/cascadelakex/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 …blicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G)…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
Duncore-io.json4 "Counter": "0,1",
11 "PerPkg": "1",
13 …a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe ca…
20 "Counter": "0,1",
27 "PerPkg": "1",
29 …a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe ca…
36 "Counter": "0,1,2,3",
39 "PerPkg": "1",
40 … "PublicDescription": "Counts clockticks of the 1GHz traffic controller clock in the IIO unit.",
45 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/skylakex/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
7 …blicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G)…
13 "Counter": "0,1,2,3",
21 …"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page wa…
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
26 …n": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.",
31 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
32 "Counter": "0,1,2,3",
35 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
[all …]
Duncore-io.json4 "Counter": "0,1",
11 "PerPkg": "1",
13 …a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe ca…
20 "Counter": "0,1",
27 "PerPkg": "1",
29 …a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe ca…
36 "Counter": "0,1,2,3",
39 "PerPkg": "1",
40 … "PublicDescription": "Counts clockticks of the 1GHz traffic controller clock in the IIO unit.",
45 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/testing/selftests/drivers/net/mlxsw/spectrum-2/
Dtc_flower.sh4 # This test is for checking the A-TCAM and C-TCAM operation in Spectrum-2.
46 local tracepoint=$1
55 local tracepoint=$1
58 perf record -a -q -e $tracepoint sleep $seconds
64 local tracepoint=$1
72 local tracepoint=$1
77 return 1
84 local tracepoint=$1
88 return 1
95 # When only a single mask is required, the device uses the master
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/s390/cf_z16/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …ion": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the reque…
21 …A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for ev…
28 …PublicDescription": "A translation entry was written into the Combined Region and Segment Table En…
35 …"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB…
42 …": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the re…
49 …A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one…
56 …"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level…
70 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
77 …"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mo…
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh4/
Dsoftfloat.c16 * of this code was written as part of a project to build a fixed-point vector
29 * (1) they include prominent notice that the work is derivative, and (2) they
42 #define LIT64( a ) a##LL argument
71 bits64 extractFloat64Frac(float64 a);
72 flag extractFloat64Sign(float64 a);
73 int16 extractFloat64Exp(float64 a);
74 int16 extractFloat32Exp(float32 a);
75 flag extractFloat32Sign(float32 a);
76 bits32 extractFloat32Frac(float32 a);
78 void shift64RightJamming(bits64 a, int16 count, bits64 * zPtr);
[all …]
/linux-6.12.1/include/drm/
Ddrm_fixed.h4 * Permission is hereby granted, free of charge, to any person obtaining a
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
37 #define dfixed_const(A) (u32)(((A) << 12))/* + ((B + 0.000122)*4096)) */ argument
38 #define dfixed_const_half(A) (u32)(((A) << 12) + 2048) argument
39 #define dfixed_const_666(A) (u32)(((A) << 12) + 2731) argument
40 #define dfixed_const_8(A) (u32)(((A) << 12) + 3277) argument
41 #define dfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12) argument
42 #define dfixed_init(A) { .full = dfixed_const((A)) } argument
43 #define dfixed_init_half(A) { .full = dfixed_const_half((A)) } argument
44 #define dfixed_trunc(A) ((A).full >> 12) argument
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/emeraldrapids/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/graniterapids/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/sapphirerapids/
Dvirtual-memory.json4 "Counter": "0,1,2,3",
12 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
13 "Counter": "0,1,2,3",
14 "CounterMask": "1",
17 …ounts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.…
22 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
23 "Counter": "0,1,2,3",
26 …s it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
31 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
32 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/haswellx/
Duncore-power.json4 "Counter": "0,1,2,3",
6 "PerPkg": "1",
7 …a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was…
12 "Counter": "0,1,2,3",
15 "PerPkg": "1",
21 "Counter": "0,1,2,3",
24 "PerPkg": "1",
30 "Counter": "0,1,2,3",
33 "PerPkg": "1",
39 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/rocketlake/
Dfrontend.json3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
4 "Counter": "0,1,2,3",
7 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
13 "Counter": "0,1,2,3",
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
33 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/icelake/
Dfrontend.json3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
4 "Counter": "0,1,2,3",
7 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
13 "Counter": "0,1,2,3",
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
33 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/x86/tigerlake/
Dfrontend.json3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
4 "Counter": "0,1,2,3",
7 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
13 "Counter": "0,1,2,3",
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
33 "Counter": "0,1,2,3",
[all …]
/linux-6.12.1/tools/perf/pmu-events/arch/s390/cf_z13/
Dextended.json7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
14 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
28 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
35 …"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookasi…
42 …"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cac…
49 …"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation …
56 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
63 …"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the retur…
70 …"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arr…
[all …]

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