Lines Matching +full:1 +full:a
3 … number when the front end is resteered, mainly when the BPU cannot provide a correct prediction a…
4 "Counter": "0,1,2,3",
7 …the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the…
13 "Counter": "0,1,2,3",
16 …to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Le…
22 "Counter": "0,1,2,3",
23 "CounterMask": "1",
24 "EdgeDetect": "1",
27 …"PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE spe…
33 "Counter": "0,1,2,3",
36 …a Uop-cache that holds translations of previously fetched instructions that were decoded by the le…
42 "Counter": "0,1,2,3,4,5,6,7",
47 "PEBS": "1",
53 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
54 "Counter": "0,1,2,3,4,5,6,7",
59 "PEBS": "1",
60 …erienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical m…
66 "Counter": "0,1,2,3,4,5,6,7",
71 "PEBS": "1",
78 "Counter": "0,1,2,3,4,5,6,7",
83 "PEBS": "1",
90 "Counter": "0,1,2,3,4,5,6,7",
95 "PEBS": "1",
101 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
102 "Counter": "0,1,2,3,4,5,6,7",
107 "PEBS": "1",
108 …rval where the front-end delivered no uops for a period of at least 1 cycle which was not interrup…
113 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
114 "Counter": "0,1,2,3,4,5,6,7",
119 "PEBS": "1",
120 …nterval where the front-end delivered no uops for a period of 128 cycles which was not interrupted…
125 …nterval where the front-end delivered no uops for a period of 16 cycles which was not interrupted …
126 "Counter": "0,1,2,3,4,5,6,7",
131 "PEBS": "1",
132 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
138 "Counter": "0,1,2,3,4,5,6,7",
143 "PEBS": "1",
144 …val where the front-end delivered no uops for a period of at least 2 cycles which was not interrup…
149 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
150 "Counter": "0,1,2,3,4,5,6,7",
155 "PEBS": "1",
156 …nterval where the front-end delivered no uops for a period of 256 cycles which was not interrupted…
161 …interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not int…
162 "Counter": "0,1,2,3,4,5,6,7",
167 "PEBS": "1",
168 …ivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A …
173 …nterval where the front-end delivered no uops for a period of 32 cycles which was not interrupted …
174 "Counter": "0,1,2,3,4,5,6,7",
179 "PEBS": "1",
180 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
185 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
186 "Counter": "0,1,2,3,4,5,6,7",
191 "PEBS": "1",
192 …interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted …
197 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
198 "Counter": "0,1,2,3,4,5,6,7",
203 "PEBS": "1",
204 …nterval where the front-end delivered no uops for a period of 512 cycles which was not interrupted…
209 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
210 "Counter": "0,1,2,3,4,5,6,7",
215 "PEBS": "1",
216 …nterval where the front-end delivered no uops for a period of 64 cycles which was not interrupted …
221 …interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted …
222 "Counter": "0,1,2,3,4,5,6,7",
227 "PEBS": "1",
228 …ion": "Counts retired instructions that are delivered to the back-end after a front-end stall of a…
234 "Counter": "0,1,2,3,4,5,6,7",
239 "PEBS": "1",
245 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This …
246 "Counter": "0,1,2,3",
249 …n": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg…
255 "Counter": "0,1,2,3",
264 "Counter": "0,1,2,3",
272 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [T…
273 "Counter": "0,1,2,3",
276 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
281 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This …
282 "Counter": "0,1,2,3",
285 …n": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The leg…
290 …"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [T…
291 "Counter": "0,1,2,3",
294 …"PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag …
300 "Counter": "0,1,2,3",
301 "CounterMask": "1",
310 "Counter": "0,1,2,3",
320 "Counter": "0,1,2,3",
329 "Counter": "0,1,2,3",
330 "CounterMask": "1",
339 "Counter": "0,1,2,3",
349 "Counter": "0,1,2,3",
358 "Counter": "0,1,2,3",
359 "CounterMask": "1",
368 "Counter": "0,1,2,3",
369 "CounterMask": "1",
370 "EdgeDetect": "1",
379 "Counter": "0,1,2,3",
388 "Counter": "0,1,2,3,4,5,6,7",
391 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
397 "Counter": "0,1,2,3,4,5,6,7",
401 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
407 "Counter": "0,1,2,3,4,5,6,7",
408 "CounterMask": "1",
411 "Invert": "1",
412 …ipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",