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/linux-6.12.1/Documentation/RCU/Design/Requirements/
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/linux-6.12.1/Documentation/RCU/Design/Memory-Ordering/
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/linux-6.12.1/Documentation/RCU/Design/Expedited-Grace-Periods/
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-usb-phy.yaml24 - description: PHY 125m
25 - description: app 125m
29 - const: 125m
48 clock-names = "125m", "app_125m";
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,qca8k-nsscc.yaml37 - description: UNIPHY0 RX 312P5M/125M clock source
38 - description: UNIPHY0 TX 312P5M/125M clock source
39 - description: UNIPHY1 RX 312P5M/125M clock source
40 - description: UNIPHY1 TX 312P5M/125M clock source
/linux-6.12.1/drivers/clk/ralink/
Dclk-mt7621.c71 GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
72 GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
73 GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
74 GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
75 GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
76 GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
78 GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
79 GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
80 GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),
82 GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)),
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