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/linux-6.12.1/arch/x86/kernel/
Dtsc_msr.c22 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
24 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
25 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
33 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
34 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
80 * 000: 100 * 5 / 6 = 83.3333 MHz
81 * 001: 100 * 1 / 1 = 100.0000 MHz
82 * 010: 100 * 4 / 3 = 133.3333 MHz
83 * 011: 100 * 7 / 6 = 116.6667 MHz
[all …]
/linux-6.12.1/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
94 mode "640x480-100"
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
/linux-6.12.1/drivers/media/i2c/et8ek8/
Det8ek8_mode.c20 * SPCK = 80 MHz
21 * CCP2 = 640 MHz
22 * VCO = 640 MHz
49 .numerator = 100,
121 * SPCK = 80 MHz
122 * CCP2 = 560 MHz
123 * VCO = 560 MHz
150 .numerator = 100,
177 * SPCK = 96.5333333333333 MHz
178 * CCP2 = 579.2 MHz
[all …]
/linux-6.12.1/drivers/cpufreq/
Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
89 #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
91 /* Use 800MHz when entering sleep mode */
129 {0, L4, 100*1000},
175 /* L0 : [1000/200/100][166/83][133/66][200/200] */
178 /* L1 : [800/200/100][166/83][133/66][200/200] */
181 /* L2 : [400/200/100][166/83][133/66][200/200] */
184 /* L3 : [200/200/100][166/83][133/66][200/200] */
187 /* L4 : [100/100/100][83/83][66/66][100/100] */
275 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 in s5pv210_target()
[all …]
Dlongrun.c56 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
58 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_get_policy()
81 pctg_lo = pctg_hi = 100; in longrun_set_policy()
84 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
86 ((longrun_high_freq - longrun_low_freq) / 100); in longrun_set_policy()
89 if (pctg_hi > 100) in longrun_set_policy()
90 pctg_hi = 100; in longrun_set_policy()
221 /* read out current core MHz and current perf_pctg */ in longrun_determine_freqs()
227 pr_debug("percentage is %u %%, freq is %u MHz\n", ecx, eax); in longrun_determine_freqs()
235 ebx = (((cpu_khz / 1000) * ecx) / 100); /* to MHz */ in longrun_determine_freqs()
[all …]
/linux-6.12.1/tools/testing/selftests/intel_pstate/
Drun.sh6 # state to the minimum supported frequency, in decrements of 100MHz. The
10 # or the requested frequency in MHz, the Actual frequency, as read from
22 #/tmp/result.3100:1:cpu MHz : 2899.980
23 #/tmp/result.3100:2:cpu MHz : 2900.000
28 # for consistency and modified to remove the extra MHz values. The result.X
65 grep MHz /proc/cpuinfo | sort -u > /tmp/result.freqs
85 # MAIN (ALL UNITS IN MHZ)
100 [ $EVALUATE_ONLY -eq 0 ] && for freq in `seq $max_freq -100 $min_freq`
103 cpupower frequency-set -g powersave --max=${freq}MHz >& /dev/null
107 [ $EVALUATE_ONLY -eq 0 ] && cpupower frequency-set -g powersave --max=${max_freq}MHz >& /dev/null
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu14_driver_if_v14_0_0.h41 uint16_t Freq; // in MHz
46 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
47 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
118 //Freq in MHz
147 //Freq in MHz
178 uint16_t CoreFrequency[16]; //Target core frequency [MHz]
185 uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz]
186 uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz]
188 uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz]
189 uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz]
[all …]
/linux-6.12.1/drivers/clk/spear/
Dspear1340_clock.c164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
/linux-6.12.1/arch/mips/jazz/
DKconfig7 This is a machine with a R4400 133/150 MHz CPU. To compile a Linux
18 This is a machine with a R4000 100 MHz CPU. To compile a Linux
28 This is a machine with a R4000 100 MHz CPU. To compile a Linux
/linux-6.12.1/drivers/media/pci/mantis/
Dmantis_vp3030.c33 .frequency_min = 47 * MHz,
34 .frequency_max = 862 * MHz,
36 .ref_multiplier = 6, /* 1/6 MHz */
37 .ref_divider = 100000, /* 1/6 MHz */
51 msleep(100); in vp3030_frontend_init()
53 msleep(100); in vp3030_frontend_init()
/linux-6.12.1/arch/powerpc/boot/dts/
Diss4xx-mpic.dts38 clock-frequency = <100000000>; // 100Mhz :-)
52 clock-frequency = <100000000>; // 100Mhz :-)
68 clock-frequency = <100000000>; // 100Mhz :-)
84 clock-frequency = <100000000>; // 100Mhz :-)
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dqcom,ipq4019-mdio.yaml42 - description: MDIO clock source frequency fixed to 100MHZ
53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
57 To follow 802.3 standard that instruct up to 2.5MHz by default, if
59 default 1.5625Mhz is select.
/linux-6.12.1/Documentation/admin-guide/pm/
Dintel-speed-select.rst154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
215 To check if the average frequency is equal to the base frequency for a 100% busy
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
425 Specify clos max in MHz with [--max|-m]
[all …]
/linux-6.12.1/drivers/platform/x86/amd/pmf/
Dpmf.h202 u16 core_frequency[16]; /* MHz */
209 u16 infra_cpu_maxfreq; /* MHz */
210 u16 infra_gfx_maxfreq; /* MHz */
212 u16 gfxclk_freq; /* MHz */
213 u16 fclk_freq; /* MHz */
214 u16 gfx_activity; /* GFX busy % [0-100] */
215 u16 socclk_freq; /* MHz */
216 u16 vclk_freq; /* MHz */
217 u16 vcn_activity; /* VCN busy % [0-100] */
218 u16 vpeclk_freq; /* MHz */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/cpu/
Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
105 entry-latency-us = <100>;
128 capacity-dmips-mhz = <1024>;
[all …]
/linux-6.12.1/arch/mips/txx9/rbtx4927/
Dsetup.c231 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4927_clock_init()
235 * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5) in rbtx4927_clock_init()
236 * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3) in rbtx4927_clock_init()
237 * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5) in rbtx4927_clock_init()
238 * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6) in rbtx4927_clock_init()
239 * i.e. S9[3]: ON (83MHz), OFF (100MHz) in rbtx4927_clock_init()
245 txx9_cpu_clock = 166666666; /* 166MHz */ in rbtx4927_clock_init()
248 txx9_cpu_clock = 200000000; /* 200MHz */ in rbtx4927_clock_init()
255 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. in rbtx4937_clock_init()
260 * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8) in rbtx4937_clock_init()
[all …]
/linux-6.12.1/drivers/phy/intel/
Dphy-intel-keembay-emmc.c59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
156 if (mhz == 0) in keembay_emmc_phy_power()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.c122 * @target_pix_clk_100hz: Desired frequency in 100 Hz
157 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ in calculate_fb_and_fractional_fb_divider()
680 * so have to divided by 100 * 100*/ in calculate_ss()
683 100 * (long long)ss_data->percentage_divider)); in calculate_ss()
992 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); in dcn31_program_pix_clk()
1097 dto_params.pixclk_hz *= 100; in dcn401_program_pix_clk()
1218 *pixel_clk_khz = clock_hz / 100; in get_pixel_clk_frequency_100hz()
1229 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17
1230 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340
1231 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dintel_llc.c63 /* convert DDR frequency from units of 266.6MHz to bandwidth */ in get_ia_constants()
84 * ring_freq = 2 * GT. ring_freq is in 100MHz units in calc_ia_freq()
89 /* max(2 * GT, DDR). NB: GT is 50MHz units */ in calc_ia_freq()
104 * For GPU frequencies less than 750MHz, in calc_ia_freq()
111 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); in calc_ia_freq()
/linux-6.12.1/tools/power/x86/turbostat/
Dturbostat.8152 \fBTSC_MHz\fP average MHz that the TSC ran during the entire interval.
190 …ary is the sum of the package throttling time, and thus may be higher than 100% on a multi-package…
194 \fBUncMHz\fP per-package uncore MHz, instantaneous sample.
196 \fBUMHz1.0\fP per-package uncore MHz for domain=1 and fabric_cluster=0, instantaneous sample. Syst…
278 TSC: 3096 MHz (24000000 Hz * 258 / 2 / 1000000)
279 CPUID(0x16): base_mhz: 3100 max_mhz: 4200 bus_mhz: 100
283 8 * 100.0 = 800.0 MHz max efficiency frequency
284 31 * 100.0 = 3100.0 MHz base frequency
287 39 * 100.0 = 3900.0 MHz max turbo 4 active cores
288 40 * 100.0 = 4000.0 MHz max turbo 3 active cores
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.c43 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed …
45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
264 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) { in smu10_set_soft_max_gfxclk_by_freq()
265 smu10_data->gfx_max_freq_limit = clock * 100; in smu10_set_soft_max_gfxclk_by_freq()
483 ptable->entries[i].clk = pclk_dependency_table->Freq * 100; in smu10_get_clock_voltage_dependency_table()
629 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; in smu10_dpm_force_dpm_level()
642 min_sclk /= 100; /* transfer 10KHz to MHz */ in smu10_dpm_force_dpm_level()
659 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
676 data->gfx_max_freq_limit/100, in smu10_dpm_force_dpm_level()
786 (data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk / 100) : in smu10_dpm_force_dpm_level()
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6sx-softing-vining-2000.dts116 max-speed = <100>;
139 max-speed = <100>;
417 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
430 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
441 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
452 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
468 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
483 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
Dimx6ull-myir-mys-6ulx.dtsi172 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
183 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
209 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
224 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
/linux-6.12.1/arch/arm/mach-omap2/
Dopp2xxx.h123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
[all …]
/linux-6.12.1/drivers/scsi/
Ddc395x.h31 #define DC395x_SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */
343 /* 000 100ns, 10.0 MHz */
344 /* 001 150ns, 6.6 MHz */
345 /* 010 200ns, 5.0 MHz */
346 /* 011 250ns, 4.0 MHz */
347 /* 100 300ns, 3.3 MHz */
348 /* 101 350ns, 2.8 MHz */
349 /* 110 400ns, 2.5 MHz */
350 /* 111 450ns, 2.2 MHz */
355 /* 000 50ns, 20.0 MHz */
[all …]

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