43 #define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed …
45 #define SMU10_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
264 	if (clock && smu10_data->gfx_max_freq_limit != (clock * 100))  {  in smu10_set_soft_max_gfxclk_by_freq()
265 		smu10_data->gfx_max_freq_limit = clock * 100;  in smu10_set_soft_max_gfxclk_by_freq()
483 		ptable->entries[i].clk         = pclk_dependency_table->Freq * 100;  in smu10_get_clock_voltage_dependency_table()
629 	uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;  in smu10_dpm_force_dpm_level()
642 	min_sclk /= 100; /* transfer 10KHz to MHz */  in smu10_dpm_force_dpm_level()
659 						data->gfx_max_freq_limit/100,  in smu10_dpm_force_dpm_level()
676 						data->gfx_max_freq_limit/100,  in smu10_dpm_force_dpm_level()
786 						(data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk / 100) :  in smu10_dpm_force_dpm_level()
792 						data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk / 100,  in smu10_dpm_force_dpm_level()
801 						data->gfx_max_freq_limit/100,  in smu10_dpm_force_dpm_level()
805 						data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk / 100,  in smu10_dpm_force_dpm_level()
809 						data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk / 100,  in smu10_dpm_force_dpm_level()
827 						data->gfx_min_freq_limit/100,  in smu10_dpm_force_dpm_level()
831 						data->gfx_min_freq_limit/100,  in smu10_dpm_force_dpm_level()
992 						low == 2 ? data->gfx_max_freq_limit/100 :  in smu10_force_clock_level()
994 						data->gfx_min_freq_limit/100,  in smu10_force_clock_level()
999 						high == 0 ? data->gfx_min_freq_limit/100 :  in smu10_force_clock_level()
1001 						data->gfx_max_freq_limit/100,  in smu10_force_clock_level()
1011 						mclk_table->entries[low].clk/100,  in smu10_force_clock_level()
1016 						mclk_table->entries[high].clk/100,  in smu10_force_clock_level()
1044 		if (now == data->gfx_max_freq_limit/100)  in smu10_print_clock_levels()
1046 		else if (now == data->gfx_min_freq_limit/100)  in smu10_print_clock_levels()
1052 					data->gfx_min_freq_limit/100,  in smu10_print_clock_levels()
1058 					data->gfx_max_freq_limit/100,  in smu10_print_clock_levels()
1069 					mclk_table->entries[i].clk / 100,  in smu10_print_clock_levels()
1070 					((mclk_table->entries[i].clk / 100)  in smu10_print_clock_levels()
1277 	clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */  in smu10_get_max_high_clocks()
1321 		*((uint32_t *)value) = sclk * 100;  in smu10_read_sensor()
1329 		*((uint32_t *)value) = mclk * 100;  in smu10_read_sensor()
1347 				*((uint32_t *)value) = min(activity_percent, (u32)100);  in smu10_read_sensor()
1566 				pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",  in smu10_set_fine_grain_clk_vol()
1577 …	pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",  in smu10_set_fine_grain_clk_vol()
1607 			pr_err("The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",  in smu10_set_fine_grain_clk_vol()