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/linux-6.12.1/Documentation/devicetree/bindings/soc/hisilicon/
Dhisilicon,hi3660-usb3-otg-bc.yaml37 reg = <0xff200000 0x1000>;
41 #phy-cells = <0>;
44 hisilicon,eye-diagram-param = <0x22466e4>;
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Daltr,msi-controller.yaml58 reg = <0xff200000 0x00000010>,
59 <0xff200010 0x00000080>;
Dqcom,pcie.yaml588 reg = <0x1b500000 0x1000>,
589 <0x1b502000 0x80>,
590 <0x1b600000 0x100>,
591 <0x0ff00000 0x100000>;
594 linux,pci-domain = <0>;
595 bus-range = <0x00 0xff>;
599 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
600 <0x82000000 0 0 0x08000000 0 0x07e00000>;
604 interrupt-map-mask = <0 0 0 0x7>;
605 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dgpio-altera.txt36 reg = <0xff200000 0x10>;
37 interrupts = <0 45 4>;
/linux-6.12.1/arch/sh/kernel/cpu/sh4a/
Dubc.c15 #define UBC_CBR(idx) (0xff200000 + (0x20 * idx))
16 #define UBC_CRR(idx) (0xff200004 + (0x20 * idx))
17 #define UBC_CAR(idx) (0xff200008 + (0x20 * idx))
18 #define UBC_CAMR(idx) (0xff20000c + (0x20 * idx))
20 #define UBC_CCMFR 0xff200600
21 #define UBC_CBCR 0xff200620
25 #define UBC_CRR_BIE (1 << 0)
28 #define UBC_CBR_CE (1 << 0)
40 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
41 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
[all …]
/linux-6.12.1/arch/m68k/sun3/
Dconfig.c62 clock_va = (char *) 0xfe06000; /* dark */ in sun3_init()
63 sun3_intreg = (unsigned char *) 0xfe0a000; /* magic */ in sun3_init()
69 enable_register |= 0x50; /* Enable FPU */ in sun3_init()
77 memset(sun3_reserved_pmeg, 0, sizeof(sun3_reserved_pmeg)); in sun3_init()
82 for (i=0; i<8; i++) /* Kernel PMEGs */ in sun3_init()
121 m68k_setup_node(0); in sun3_bootmem_alloc()
142 memory_start = ((((unsigned long)_end) + 0x2000) & ~0x1fff); in config_sun3()
147 m68k_memory[0].size=*(romvec->pv_sun3mem); in config_sun3()
173 .start = 0xff200000,
174 .end = 0xff200021,
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dp1023rdb.dts56 size = <0 0x1000000>;
57 alignment = <0 0x1000000>;
60 size = <0 0x400000>;
61 alignment = <0 0x400000>;
64 size = <0 0x2000000>;
65 alignment = <0 0x2000000>;
70 ranges = <0x0 0xf 0xff000000 0x200000>;
74 ranges = <0x0 0xf 0xff200000 0x200000>;
78 ranges = <0x0 0x0 0xff600000 0x200000>;
83 reg = <0x53>;
[all …]
/linux-6.12.1/include/linux/ssb/
Dssb_regs.h9 #define SSB_SDRAM_BASE 0x00000000U /* Physical SDRAM */
10 #define SSB_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
11 #define SSB_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
12 #define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
13 #define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */
14 #define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */
16 #define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
17 #define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */
19 #define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */
20 #define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/hisilicon/
Dhi3660.dtsi25 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0 0x0>;
75 reg = <0x0 0x1>;
88 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
114 reg = <0x0 0x100>;
128 reg = <0x0 0x101>;
141 reg = <0x0 0x102>;
154 reg = <0x0 0x103>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Dpx30.dtsi39 #size-cells = <0>;
41 cpu0: cpu@0 {
44 reg = <0x0 0x0>;
56 reg = <0x0 0x1>;
68 reg = <0x0 0x2>;
80 reg = <0x0 0x3>;
95 arm,psci-suspend-param = <0x0010000>;
104 arm,psci-suspend-param = <0x1010000>;
112 cpu0_opp_table: opp-table-0 {
163 #clock-cells = <0>;
[all …]
Drk3399-base.dtsi51 #size-cells = <0>;
79 cpu_l0: cpu@0 {
82 reg = <0x0 0x0>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x1>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
120 reg = <0x0 0x2>;
127 i-cache-size = <0x8000>;
[all …]