cpu/sh4a/ubc.c

15 #define UBC_CBR(idx)	(0xff200000 + (0x20 * idx))
16 #define UBC_CRR(idx)	(0xff200004 + (0x20 * idx))
17 #define UBC_CAR(idx)	(0xff200008 + (0x20 * idx))
18 #define UBC_CAMR(idx)	(0xff20000c + (0x20 * idx))
20 #define UBC_CCMFR	0xff200600
21 #define UBC_CBCR	0xff200620
25 #define UBC_CRR_BIE	(1 << 0)
28 #define UBC_CBR_CE	(1 << 0)
40 	__raw_writel(0, UBC_CBR(idx));  in sh4a_ubc_disable()
41 	__raw_writel(0, UBC_CAR(idx));  in sh4a_ubc_disable()
48 	for (i = 0; i < sh4a_ubc.num_events; i++)  in sh4a_ubc_enable_all()
58 	for (i = 0; i < sh4a_ubc.num_events; i++)  in sh4a_ubc_disable_all()
65 	unsigned long active = 0;  in sh4a_ubc_active_mask()
68 	for (i = 0; i < sh4a_ubc.num_events; i++)  in sh4a_ubc_active_mask()
88 	.trap_nr		= 0x1e0,
112 	__raw_writel(0, UBC_CBCR);  in sh4a_ubc_init()
114 	for (i = 0; i < sh4a_ubc.num_events; i++) {  in sh4a_ubc_init()
115 		__raw_writel(0, UBC_CAMR(i));  in sh4a_ubc_init()
116 		__raw_writel(0, UBC_CBR(i));  in sh4a_ubc_init()