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/linux-6.12.1/drivers/watchdog/
Dsp5100_tco.h15 #define SP5100_WDT_MEM_MAP_SIZE 0x08
16 #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
17 #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
19 #define SP5100_WDT_START_STOP_BIT BIT(0)
25 #define SP5100_PM_IOPORTS_SIZE 0x02
33 #define SP5100_IO_PM_INDEX_REG 0xCD6
34 #define SP5100_IO_PM_DATA_REG 0xCD7
37 #define SP5100_SB_RESOURCE_MMIO_BASE 0x9C
39 #define SP5100_PM_WATCHDOG_CONTROL 0x69
40 #define SP5100_PM_WATCHDOG_BASE 0x6C
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Drenesas,dsi-csi2-tx.yaml48 port@0:
71 - port@0
91 reg = <0xfed80000 0x10000>;
101 #size-cells = <0>;
103 port@0 {
104 reg = <0>;
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dphy-rockchip-usbdp.yaml62 <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
131 reg = <0xfed80000 0x10000>;
/linux-6.12.1/drivers/gpio/
Dgpio-amd-fch.c20 #define AMD_FCH_MMIO_BASE 0xFED80000
21 #define AMD_FCH_GPIO_BANK0_BASE 0x1500
22 #define AMD_FCH_GPIO_SIZE 0x0300
58 return 0; in amd_fch_gpio_direction_input()
81 return 0; in amd_fch_gpio_direction_output()
136 return 0; in amd_fch_gpio_request()
/linux-6.12.1/drivers/leds/
Dleds-apu.c45 #define APU1_FCH_ACPI_MMIO_BASE 0xFED80000
46 #define APU1_FCH_GPIO_BASE (APU1_FCH_ACPI_MMIO_BASE + 0x01BD)
47 #define APU1_LEDON 0x08
48 #define APU1_LEDOFF 0xC8
80 { "apu:green:1", LED_ON, APU1_FCH_GPIO_BASE + 0 * APU1_IOSIZE },
127 for (i = 0; i < ARRAY_SIZE(apu1_led_profile); i++) { in apu_led_config()
151 return 0; in apu_led_config()
154 while (i-- > 0) in apu_led_config()
189 pdev = platform_device_register_simple(KBUILD_MODNAME, -1, NULL, 0); in apu_led_init()
208 for (i = 0; i < ARRAY_SIZE(apu1_led_profile); i++) in apu_led_exit()
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-usbdp.c29 #define UDPHY_PCS 0x4000
30 #define UDPHY_PMA 0x8000
38 #define DP_LANE_SEL_ALL GENMASK(7, 0)
41 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
45 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
47 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
51 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
53 #define CMN_LCPLL_SSC_EN BIT(0)
55 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
59 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr8a779g0.dtsi20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
88 a76_0: cpu@0 {
90 reg = <0>;
102 reg = <0x100>;
114 reg = <0x10000>;
[all …]
Dr8a779a0.dtsi20 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #size-cells = <0>;
28 a76_0: cpu@0 {
30 reg = <0>;
37 L3_CA76_0: cache-controller-0 {
47 #clock-cells = <0>;
49 clock-frequency = <0>;
54 #clock-cells = <0>;
56 clock-frequency = <0>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3588-base.dtsi56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
115 reg = <0x100>;
134 reg = <0x200>;
153 reg = <0x300>;
172 reg = <0x400>;
193 reg = <0x500>;
212 reg = <0x600>;
233 reg = <0x700>;
[all …]