Lines Matching +full:0 +full:xfed80000

15 #define SP5100_WDT_MEM_MAP_SIZE		0x08
16 #define SP5100_WDT_CONTROL(base)	((base) + 0x00) /* Watchdog Control */
17 #define SP5100_WDT_COUNT(base)		((base) + 0x04) /* Watchdog Count */
19 #define SP5100_WDT_START_STOP_BIT	BIT(0)
25 #define SP5100_PM_IOPORTS_SIZE		0x02
33 #define SP5100_IO_PM_INDEX_REG		0xCD6
34 #define SP5100_IO_PM_DATA_REG		0xCD7
37 #define SP5100_SB_RESOURCE_MMIO_BASE	0x9C
39 #define SP5100_PM_WATCHDOG_CONTROL	0x69
40 #define SP5100_PM_WATCHDOG_BASE		0x6C
42 #define SP5100_PCI_WATCHDOG_MISC_REG	0x41
45 #define SP5100_PM_WATCHDOG_DISABLE	((u8)BIT(0))
51 #define SB800_PM_ACPI_MMIO_EN		0x24
52 #define SB800_PM_WATCHDOG_CONTROL	0x48
53 #define SB800_PM_WATCHDOG_BASE		0x48
54 #define SB800_PM_WATCHDOG_CONFIG	0x4C
56 #define SB800_PCI_WATCHDOG_DECODE_EN	BIT(0)
58 #define SB800_PM_WATCHDOG_SECOND_RES	GENMASK(1, 0)
59 #define SB800_ACPI_MMIO_DECODE_EN	BIT(0)
61 #define SB800_ACPI_MMIO_MASK		GENMASK(1, 0)
63 #define SB800_PM_WDT_MMIO_OFFSET	0xB00
69 #define EFCH_PM_DECODEEN		0x00
74 #define EFCH_PM_DECODEEN3		0x03
75 #define EFCH_PM_DECODEEN_SECOND_RES	GENMASK(1, 0)
79 #define EFCH_PM_WDT_ADDR		0xfeb00000
81 #define EFCH_PM_ISACONTROL		0x04
85 #define EFCH_PM_ACPI_MMIO_ADDR		0xfed80000
86 #define EFCH_PM_ACPI_MMIO_PM_OFFSET	0x00000300
87 #define EFCH_PM_ACPI_MMIO_WDT_OFFSET	0x00000b00
92 #define AMD_ZEN_SMBUS_PCI_REV		0x51