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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Drockchip,rk3576-cru.yaml53 reg = <0xfd7c0000 0x5c000>;
Drockchip,rk3588-cru.yaml64 reg = <0xfd7c0000 0x5c000>;
/linux-6.12.1/drivers/clk/rockchip/
Drst-rk3588.c13 /* 0xFD7C0000 + 0x0A00 */
14 #define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
16 /* 0xFD7C8000 + 0x0A00 */
17 #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
19 /* 0xFD7D0000 + 0x0A00 */
20 #define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
22 /* 0xFD7F0000 + 0x0A00 */
23 #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
37 RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0),
48 RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0),
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3588-base.dtsi56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
115 reg = <0x100>;
134 reg = <0x200>;
153 reg = <0x300>;
172 reg = <0x400>;
193 reg = <0x500>;
212 reg = <0x600>;
233 reg = <0x700>;
[all …]