clk/rockchip/rst-rk3588.c

13 /* 0xFD7C0000 + 0x0A00 */
14 #define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
16 /* 0xFD7C8000 + 0x0A00 */
17 #define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
19 /* 0xFD7D0000 + 0x0A00 */
20 #define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
22 /* 0xFD7F0000 + 0x0A00 */
23 #define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
37 	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0),
48 	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0),
56 	RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM
68 	RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0),
75 	RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0),
89 	RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0),
119 	RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0),
136 	RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0),
150 	RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0),
172 	RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0),
186 	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0),
204 	RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0),
221 	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0),
233 	RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0),
238 	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0),
256 	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0),
270 	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0),
281 	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0),
299 	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0),
313 	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0),
330 	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0),
336 	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0),
354 	RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0),
389 	RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0),
397 	RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0),
452 	RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0),
471 	RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0),
510 	RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0),
540 	RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0),
589 	RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0),
599 	RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0),
607 	RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0),
628 	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0),
636 	RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0),
654 	RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0),
677 	RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0),
708 	RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM
744 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1),
745 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2),
746 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3),
747 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4),
748 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5),
749 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6),
750 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7),
751 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8),
752 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9),
753 	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10),
756 	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10),
757 	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11),
758 	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12),
759 	RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13),
760 	RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14),
787 	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0),
794 	RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0),
812 	RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10),
813 	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
814 	RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12),
815 	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13),
816 	RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14),
817 	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15),
820 	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0),
833 	RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0),
842 	RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0),
856 				      reg_base + RK3588_SOFTRST_CON(0),  in rk3588_rst_init()