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Searched +full:0 +full:xe450 (Results 1 – 5 of 5) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/phy/
Drockchip,inno-usb2phy.yaml7 title: Rockchip USB2.0 phy with inno IP block
34 const: 0
81 const: 0
104 const: 0
184 reg = <0xe450 0x10>;
188 #clock-cells = <0>;
191 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
193 #phy-cells = <0>;
197 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
198 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
[all …]
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-inno-usb2.c3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
43 PHY_STATE_HS_ONLINE = 0,
62 USB_CHG_STATE_UNDEFINED = 0,
228 * struct rockchip_usb2phy - usb2.0 phy driver data.
310 return 0; in rockchip_usb2phy_reset()
330 return 0; in rockchip_usb2phy_clk480m_prepare()
380 int ret = 0; in rockchip_usb2phy_clk480m_register()
382 init.flags = 0; in rockchip_usb2phy_clk480m_register()
395 init.num_parents = 0; in rockchip_usb2phy_clk480m_register()
408 if (ret < 0) in rockchip_usb2phy_clk480m_register()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.yaml57 description: Use rockchip,rk3588-vo{0,1}-grf instead.
201 "^phy@[0-9a-f]+$":
245 "usb2phy@[0-9a-f]+$":
306 reg = <0xff770000 0x10000>;
317 #phy-cells = <0>;
322 reg = <0xf780 0x20>;
326 #phy-cells = <0>;
331 reg = <0xe450 0x10>;
334 #clock-cells = <0>;
338 #phy-cells = <0>;
[all …]
/linux-6.12.1/drivers/mfd/
Dintel-lpss-pci.c29 PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1182),
34 PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1237),
39 PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x51fb, 0x1028, 0x0beb),
58 if (ret < 0) in intel_lpss_pci_probe()
66 info->mem = pci_resource_n(pdev, 0); in intel_lpss_pci_probe()
67 info->irq = pci_irq_vector(pdev, 0); in intel_lpss_pci_probe()
73 pdev->d3cold_delay = 0; in intel_lpss_pci_probe()
86 return 0; in intel_lpss_pci_probe()
250 { PCI_VDEVICE(INTEL, 0x02a8), (kernel_ulong_t)&spt_uart_info },
251 { PCI_VDEVICE(INTEL, 0x02a9), (kernel_ulong_t)&spt_uart_info },
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3399-base.dtsi51 #size-cells = <0>;
79 cpu_l0: cpu@0 {
82 reg = <0x0 0x0>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
101 reg = <0x0 0x1>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
120 reg = <0x0 0x2>;
127 i-cache-size = <0x8000>;
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