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/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dpq3-dma-1.dtsi2 * PQ3 DMA device tree stub [ controller @ offset 0xc300 ]
39 reg = <0xc300 0x4>;
40 ranges = <0x0 0xc100 0x200>;
42 dma-channel@0 {
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <76 2 0 0>;
50 reg = <0x80 0x80>;
52 interrupts = <77 2 0 0>;
56 reg = <0x100 0x80>;
[all …]
/linux-6.12.1/drivers/net/phy/
Dqt2025.rs40 const PHY_DEVICE_ID: phy::DeviceId = phy::DeviceId::new_with_exact_mask(0x0043a400);
44 // Only 0x3b works with this driver and firmware. in probe()
45 let hw_rev = dev.read(C45::new(Mmd::PMAPMD, 0xd001))?; in probe()
46 if (hw_rev >> 8) != 0xb3 { in probe()
51 dev.write(C45::new(Mmd::PMAPMD, 0xc300), 0x0000)?; in probe()
53 dev.write(C45::new(Mmd::PMAPMD, 0xc302), 0x0004)?; in probe()
55 dev.write(C45::new(Mmd::PMAPMD, 0xc319), 0x0038)?; in probe()
57 dev.write(C45::new(Mmd::PMAPMD, 0xc31a), 0x0098)?; in probe()
61 dev.write(C45::new(Mmd::PCS, 0x0026), 0x0e00)?; in probe()
62 dev.write(C45::new(Mmd::PCS, 0x0027), 0x0893)?; in probe()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/apm/
Dapm-storm.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0x0 0x000>;
23 cpu-release-addr = <0x1 0x0000fff8>;
29 reg = <0x0 0x001>;
31 cpu-release-addr = <0x1 0x0000fff8>;
37 reg = <0x0 0x100>;
39 cpu-release-addr = <0x1 0x0000fff8>;
45 reg = <0x0 0x101>;
47 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/linux-6.12.1/drivers/dma/ti/
Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
Dk3-psil-am62.c73 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
74 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
75 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
76 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
78 PSIL_PDMA_XY_PKT(0x4300),
79 PSIL_PDMA_XY_PKT(0x4301),
80 PSIL_PDMA_XY_PKT(0x4302),
81 PSIL_PDMA_XY_PKT(0x4303),
82 PSIL_PDMA_XY_PKT(0x4304),
83 PSIL_PDMA_XY_PKT(0x4305),
[all …]
Dk3-psil-am62a.c83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
Dk3-psil-am62p.c83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_guc_regs.h16 #define DIST_DBS_POPULATED XE_REG(0xd08)
18 #define SQIDIS_DOORBELL_EXIST_MASK REG_GENMASK(15, 0)
20 #define DRBREGL(x) XE_REG(0x1000 + (x) * 8)
21 #define DRB_VALID REG_BIT(0)
22 #define DRBREGU(x) XE_REG(0x1000 + (x) * 8 + 4)
24 #define GTCR XE_REG(0x4274)
25 #define GTCR_INVALIDATE REG_BIT(0)
27 #define GUC_ARAT_C6DIS XE_REG(0xa178)
29 #define GUC_STATUS XE_REG(0xc000)
31 #define GS_AUTH_STATUS_BAD REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x1)
[all …]
/linux-6.12.1/drivers/staging/media/meson/vdec/
Dhevc_regs.h9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_reg.h16 #define GUC_STATUS _MMIO(0xc000)
17 #define GS_RESET_SHIFT 0
18 #define GS_MIA_IN_RESET (0x01 << GS_RESET_SHIFT)
20 #define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
22 #define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
24 #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
25 #define GS_MIA_CORE_STATE (0x01 << GS_MIA_SHIFT)
26 #define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT)
27 #define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT)
29 #define GS_AUTH_STATUS_MASK (0x03U << GS_AUTH_STATUS_SHIFT)
[all …]
/linux-6.12.1/drivers/net/ethernet/sfc/falcon/
Dqt202x_phy.c28 #define MDIO_QUAKE_LED0_REG (0xD006)
31 #define PCS_FW_HEARTBEAT_REG 0xd7ee
32 #define PCS_FW_HEARTB_LBN 0
34 #define PCS_FW_PRODUCT_CODE_1 0xd7f0
35 #define PCS_FW_VERSION_1 0xd7f3
36 #define PCS_FW_BUILD_1 0xd7f6
37 #define PCS_UC8051_STATUS_REG 0xd7fd
38 #define PCS_UC_STATUS_LBN 0
40 #define PCS_UC_STATUS_FW_SAVE 0x20
41 #define PMA_PMD_MODE_REG 0xc301
[all …]
/linux-6.12.1/sound/soc/codecs/
Drt1318-sdw.c24 { 0xc001, 0x43 },
25 { 0xc003, 0xa2 },
26 { 0xc004, 0x44 },
27 { 0xc005, 0x44 },
28 { 0xc006, 0x33 },
29 { 0xc007, 0x64 },
30 { 0xc320, 0x20 },
31 { 0xf203, 0x18 },
32 { 0xf211, 0x00 },
33 { 0xf212, 0x26 },
[all …]
Drt1017-sdca-sdw.h18 #define FUNC_NUM_SMART_AMP 0x04
21 #define RT1017_SDCA_ENT_PDE23 0x31
22 #define RT1017_SDCA_ENT_PDE22 0x33
23 #define RT1017_SDCA_ENT_CS21 0x21
24 #define RT1017_SDCA_ENT_SAPU29 0x29
25 #define RT1017_SDCA_ENT_XU22 0x22
26 #define RT1017_SDCA_ENT_FU 0x03
27 #define RT1017_SDCA_ENT_UDMPU21 0x02
30 #define RT1017_SDCA_CTL_FS_INDEX 0x10
31 #define RT1017_SDCA_CTL_REQ_POWER_STATE 0x01
[all …]
Drt1017-sdca-sdw.c27 case 0x2f55: in rt1017_sdca_readable_register()
28 case 0x3206: in rt1017_sdca_readable_register()
29 case 0xc000: in rt1017_sdca_readable_register()
30 case 0xc001: in rt1017_sdca_readable_register()
31 case 0xc022: in rt1017_sdca_readable_register()
32 case 0xc030: in rt1017_sdca_readable_register()
33 case 0xc104: in rt1017_sdca_readable_register()
34 case 0xc10b: in rt1017_sdca_readable_register()
35 case 0xc10c: in rt1017_sdca_readable_register()
36 case 0xc110: in rt1017_sdca_readable_register()
[all …]
Drt1308-sdw.c31 case 0x00e0: in rt1308_readable_register()
32 case 0x00f0: in rt1308_readable_register()
33 case 0x2f01 ... 0x2f07: in rt1308_readable_register()
34 case 0x3000 ... 0x3001: in rt1308_readable_register()
35 case 0x3004 ... 0x3005: in rt1308_readable_register()
36 case 0x3008: in rt1308_readable_register()
37 case 0x300a: in rt1308_readable_register()
38 case 0xc000 ... 0xcff3: in rt1308_readable_register()
48 case 0x2f01 ... 0x2f07: in rt1308_volatile_register()
49 case 0x3000 ... 0x3001: in rt1308_volatile_register()
[all …]
Drt1318.c34 { 0x0000C000, 0x01},
35 { 0x0000F20D, 0x00},
36 { 0x0000F212, 0x3E},
37 { 0x0000C001, 0x02},
38 { 0x0000C003, 0x22},
39 { 0x0000C004, 0x44},
40 { 0x0000C005, 0x44},
41 { 0x0000C007, 0x64},
42 { 0x0000C00E, 0xE7},
43 { 0x0000F223, 0x7F},
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am654-icssg2.dtso16 ethernet1 = "/icssg2-eth/ethernet-ports/port@0";
24 pinctrl-0 = <&icssg2_rgmii_pins_default>;
47 interrupts = <24 0 2>, <25 1 3>;
50 dmas = <&main_udmap 0xc300>, /* egress slice 0 */
51 <&main_udmap 0xc301>, /* egress slice 0 */
52 <&main_udmap 0xc302>, /* egress slice 0 */
53 <&main_udmap 0xc303>, /* egress slice 0 */
54 <&main_udmap 0xc304>, /* egress slice 1 */
55 <&main_udmap 0xc305>, /* egress slice 1 */
56 <&main_udmap 0xc306>, /* egress slice 1 */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/
Dti,icssg-prueth.yaml21 - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0
35 - const: tx0-0
39 - const: tx1-0
92 const: 0
95 ^port@[0-1]$:
104 - enum: [0, 1]
131 - port@0
170 /* Example k3-am654 base board SR2.0, dual-emac */
174 pinctrl-0 = <&icssg2_rgmii_pins_default>;
191 dmas = <&main_udmap 0xc300>, /* egress slice 0 */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm4908.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
31 reg = <0x0>;
33 cpu-release-addr = <0x0 0xfff8>;
40 reg = <0x1>;
42 cpu-release-addr = <0x0 0xfff8>;
49 reg = <0x2>;
51 cpu-release-addr = <0x0 0xfff8>;
58 reg = <0x3>;
60 cpu-release-addr = <0x0 0xfff8>;
[all …]
/linux-6.12.1/include/linux/mfd/
Didt8a340_reg.h3 * Based on 5.2.0, Family Programming Guide (Sept 30, 2020)
10 #define PAGE_ADDR_BASE 0x0000
11 #define PAGE_ADDR 0x00fc
13 #define HW_REVISION 0x8180
14 #define REV_ID 0x007a
16 #define HW_DPLL_0 (0x8a00)
17 #define HW_DPLL_1 (0x8b00)
18 #define HW_DPLL_2 (0x8c00)
19 #define HW_DPLL_3 (0x8d00)
20 #define HW_DPLL_4 (0x8e00)
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dxpedite5301.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
[all …]
Dxpedite5370.dts27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
[all …]
Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
Dxpedite5330.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
30 #size-cells = <0>;
32 pmcslot@0 {
33 cell-index = <0>;
44 #size-cells = <0>;
46 xmcslot@0 {
47 cell-index = <0>;
65 #size-cells = <0>;
67 PowerPC,8572@0 {
69 reg = <0x0>;
[all …]
/linux-6.12.1/arch/mips/include/asm/sn/
Dioc3.h30 u8 iu_ier; /* DLAB == 0 */
34 u8 iu_rbr; /* read only, DLAB == 0 */
35 u8 iu_thr; /* write only, DLAB == 0 */
45 u8 fill[0x141]; /* starts at 0x141 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
69 struct ioc3_uartregs uartb; /* 0x20170 */
70 struct ioc3_uartregs uarta; /* 0x20178 */
[all …]

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