Lines Matching +full:0 +full:xc300

16 #define GUC_STATUS			_MMIO(0xc000)
17 #define GS_RESET_SHIFT 0
18 #define GS_MIA_IN_RESET (0x01 << GS_RESET_SHIFT)
20 #define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
22 #define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
24 #define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
25 #define GS_MIA_CORE_STATE (0x01 << GS_MIA_SHIFT)
26 #define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT)
27 #define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT)
29 #define GS_AUTH_STATUS_MASK (0x03U << GS_AUTH_STATUS_SHIFT)
30 #define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT)
31 #define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT)
33 #define GUC_HEADER_INFO _MMIO(0xc014)
35 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
38 #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
39 #define MEDIA_SOFT_SCRATCH(n) _MMIO(0x190310 + (n) * 4)
42 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
45 #define DMA_ADDR_0_LOW _MMIO(0xc300)
46 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
47 #define DMA_ADDR_1_LOW _MMIO(0xc308)
48 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
51 #define DMA_COPY_SIZE _MMIO(0xc310)
52 #define DMA_CTRL _MMIO(0xc314)
55 #define START_DMA (1<<0)
56 #define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
57 #define GUC_WOPCM_OFFSET_VALID (1<<0)
58 #define HUC_LOADING_AGENT_VCR (0<<1)
61 #define GUC_WOPCM_OFFSET_MASK (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
62 #define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
64 #define HUC_STATUS2 _MMIO(0xD3B0)
67 #define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)
68 #define HUC_LOAD_SUCCESSFUL (1 << 0)
70 #define GUC_WOPCM_SIZE _MMIO(0xc050)
71 #define GUC_WOPCM_SIZE_LOCKED (1<<0)
73 #define GUC_WOPCM_SIZE_MASK (0xfffff << GUC_WOPCM_SIZE_SHIFT)
75 #define GEN8_GT_PM_CONFIG _MMIO(0x138140)
76 #define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
77 #define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
78 #define GT_DOORBELL_ENABLE (1<<0)
80 #define GEN8_GTCR _MMIO(0x4274)
81 #define GEN8_GTCR_INVALIDATE (1<<0)
83 #define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)
84 #define GEN12_GUC_TLB_INV_CR_INVALIDATE (1 << 0)
86 #define GUC_ARAT_C6DIS _MMIO(0xA178)
88 #define GUC_SHIM_CONTROL _MMIO(0xc064)
89 #define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
98 #define GUC_SHIM_CONTROL2 _MMIO(0xc068)
102 #define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
103 #define GUC_SEND_TRIGGER (1<<0)
104 #define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
105 #define MEDIA_GUC_HOST_INTERRUPT _MMIO(0x190304)
107 #define GEN12_GUC_SEM_INTR_ENABLES _MMIO(0xc71c)
109 #define GUC_SEM_INTR_ENABLE_ALL (0xff)
116 #define GUC_DOORBELL_DISABLED 0
123 #define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
124 #define GEN8_DRB_VALID (1<<0)
125 #define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
127 #define GEN12_DIST_DBS_POPULATED _MMIO(0xd08)
129 #define GEN12_DOORBELLS_PER_SQIDI (0xff)
130 #define GEN12_SQIDIS_DOORBELL_EXIST (0xffff)
132 #define DE_GUCRMR _MMIO(0x44054)
134 #define GUC_BCS_RCS_IER _MMIO(0xC550)
135 #define GUC_VCS2_VCS1_IER _MMIO(0xC554)
136 #define GUC_WD_VECS_IER _MMIO(0xC558)
137 #define GUC_PM_P24C_IER _MMIO(0xC55C)
155 #define GUC_INTR_SW_INT_0 BIT(0)