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/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
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Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dat91-wb50n.dtsi21 reg = <0x20000000 0x4000000>;
51 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
53 slot@0 {
54 reg = <0>;
61 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
63 atheros@0 {
66 reg = <0>;
76 dmas = <0>, <0>; /* Do not use DMA for dbgu */
84 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts_cts>;
92 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/vf/
Dvf610m4-colibri.dts22 reg = <0x8c000000 0x3000000>;
48 pinctrl-0 = <&pinctrl_uart2>;
56 VF610_PAD_PTD0__UART2_TX 0x21a2
57 VF610_PAD_PTD1__UART2_RX 0x21a1
58 VF610_PAD_PTD2__UART2_RTS 0x21a2
59 VF610_PAD_PTD3__UART2_CTS 0x21a1
/linux-6.12.1/arch/riscv/boot/dts/microchip/
Dmpfs-polarberry-fabric.dtsi7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
25 bus-range = <0x0 0x7f>;
28 interrupt-map = <0 0 0 1 &pcie_intc 0>,
29 <0 0 0 2 &pcie_intc 1>,
30 <0 0 0 3 &pcie_intc 2>,
[all …]
Dmpfs-m100pfs-fabric.dtsi7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
25 bus-range = <0x0 0x7f>;
28 interrupt-map = <0 0 0 1 &pcie_intc 0>,
29 <0 0 0 2 &pcie_intc 1>,
30 <0 0 0 3 &pcie_intc 2>,
[all …]
Dmpfs-icicle-kit-fabric.dtsi10 reg = <0x0 0x40000000 0x0 0xF0>;
11 microchip,sync-update-mask = /bits/ 32 <0>;
19 reg = <0x0 0x40000200 0x0 0x100>;
21 #size-cells = <0>;
31 #address-cells = <0x3>;
32 #interrupt-cells = <0x1>;
33 #size-cells = <0x2>;
35 reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
37 bus-range = <0x0 0x7f>;
40 interrupt-map = <0 0 0 1 &pcie_intc 0>,
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dsifive,fu540-c000-pdma.yaml23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
69 reg = <0x3000000 0x8000>;
/linux-6.12.1/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/vce/
Dvce_3_0_sh_mask.h27 #define VCE_STATUS__JOB_BUSY_MASK 0x1
28 #define VCE_STATUS__JOB_BUSY__SHIFT 0x0
29 #define VCE_STATUS__VCPU_REPORT_MASK 0xfe
30 #define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
31 #define VCE_STATUS__UENC_BUSY_MASK 0x100
32 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
33 #define VCE_STATUS__VCE_CONFIGURATION_MASK 0xc00000
34 #define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
35 #define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x3000000
36 #define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
[all …]
/linux-6.12.1/drivers/dma/sf-pdma/
Dsf-pdma.h13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
27 #define PDMA_BASE_ADDR 0x3000000
28 #define PDMA_CHAN_OFFSET 0x1000
31 #define PDMA_CTRL 0x000
32 #define PDMA_XFER_TYPE 0x004
33 #define PDMA_XFER_SIZE 0x008
34 #define PDMA_DST_ADDR 0x010
35 #define PDMA_SRC_ADDR 0x018
36 #define PDMA_ACT_TYPE 0x104 /* Read-only */
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_11_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
Ddce_10_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
Ddce_11_2_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0.dtsi39 ranges = <0x0 0x0 0xe8000000 0x4000000>;
51 reg = <0x3000000 0x10000>, /* GICD */
52 <0x3060000 0x100000>, /* GICR */
53 <0x00c0000 0x2000>, /* GICC */
54 <0x00d0000 0x1000>, /* GICH */
55 <0x00e0000 0x2000>; /* GICV */
61 reg = <0x3040000 0x20000>;
75 reg = <0x400000 0x1000>,
76 <0x410000 0x1000>;
77 msi-parent = <&gic_its_ap0 0xa0>;
[all …]
/linux-6.12.1/arch/x86/pci/
Dolpc.c33 * the size of the region by writing ~0 to a base address register
38 * ~0 to a base address register.
41 static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
42 0x0, 0x0, 0x0, 0x0,
43 0x0, 0x0, 0x0, 0x0,
45 0x281022, 0x2200005, 0x6000021, 0x80f808, /* AMD Vendor ID */
46 0x0, 0x0, 0x0, 0x0, /* No virtual registers, hence no BAR */
47 0x0, 0x0, 0x0, 0x28100b,
48 0x0, 0x0, 0x0, 0x0,
49 0x0, 0x0, 0x0, 0x0,
[all …]
/linux-6.12.1/drivers/net/ethernet/ezchip/
Dnps_enet.h10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/sram/
Dallwinner,sun4i-a10-system-control.yaml59 "^regulators@[0-9a-f]+$":
118 reg = <0x01c00000 0x30>;
123 sram_a: sram@0 {
125 reg = <0x00000000 0xc000>;
128 ranges = <0 0x00000000 0xc000>;
132 reg = <0x8000 0x4000>;
140 reg = <0x3000000 0x1000>;
147 reg = <0x3000150 0x4>;

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