33  * the size of the region by writing ~0 to a base address register
38  * ~0 to a base address register.
41 static const uint32_t lxnb_hdr[] = {  /* dev 1 function 0 - devfn = 8 */
42 	0x0,	0x0,	0x0,	0x0,
43 	0x0,	0x0,	0x0,	0x0,
45 	0x281022, 0x2200005, 0x6000021, 0x80f808,	/* AMD Vendor ID */
46 	0x0,	0x0,	0x0,	0x0,   /* No virtual registers, hence no BAR */
47 	0x0,	0x0,	0x0,	0x28100b,
48 	0x0,	0x0,	0x0,	0x0,
49 	0x0,	0x0,	0x0,	0x0,
50 	0x0,	0x0,	0x0,	0x0,
51 	0x0,	0x0,	0x0,	0x0,
54 static const uint32_t gxnb_hdr[] = {  /* dev 1 function 0 - devfn = 8 */
55 	0xfffffffd, 0x0, 0x0,	0x0,
56 	0x0,	0x0,	0x0,	0x0,
58 	0x28100b, 0x2200005, 0x6000021, 0x80f808,	/* NSC Vendor ID */
59 	0xac1d,	0x0,	0x0,	0x0,  /* I/O BAR - base of virtual registers */
60 	0x0,	0x0,	0x0,	0x28100b,
61 	0x0,	0x0,	0x0,	0x0,
62 	0x0,	0x0,	0x0,	0x0,
63 	0x0,	0x0,	0x0,	0x0,
64 	0x0,	0x0,	0x0,	0x0,
68 	0xff000008, 0xffffc000, 0xffffc000, 0xffffc000,
69 	0xffffc000,	0x0,	0x0,	0x0,
71 	0x20811022, 0x2200003, 0x3000000, 0x0,		/* AMD Vendor ID */
72 	0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000, /* FB, GP, VG, DF */
73 	0xfe00c000, 0x0, 0x0,	0x30100b,		/* VIP */
74 	0x0,	0x0,	0x0,	0x10e,	   /* INTA, IRQ14 for graphics accel */
75 	0x0,	0x0,	0x0,	0x0,
76 	0x3d0,	0x3c0,	0xa0000, 0x0,	    /* VG IO, VG IO, EGA FB, MONO FB */
77 	0x0,	0x0,	0x0,	0x0,
81 	0xff800008, 0xffffc000, 0xffffc000, 0xffffc000,
82 	0x0,	0x0,	0x0,	0x0,
84 	0x30100b, 0x2200003, 0x3000000, 0x0,		/* NSC Vendor ID */
85 	0xfd000000, 0xfe000000, 0xfe004000, 0xfe008000,	/* FB, GP, VG, DF */
86 	0x0,	0x0,	0x0,	0x30100b,
87 	0x0,	0x0,	0x0,	0x0,
88 	0x0,	0x0,	0x0,	0x0,
89 	0x3d0,	0x3c0,	0xa0000, 0x0,  	    /* VG IO, VG IO, EGA FB, MONO FB */
90 	0x0,	0x0,	0x0,	0x0,
93 static const uint32_t aes_hdr[] = {	/* dev 1 function 2 - devfn = 0xa */
94 	0xffffc000, 0x0, 0x0,	0x0,
95 	0x0,	0x0,	0x0,	0x0,
97 	0x20821022, 0x2a00006, 0x10100000, 0x8,		/* NSC Vendor ID */
98 	0xfe010000, 0x0, 0x0,	0x0,			/* AES registers */
99 	0x0,	0x0,	0x0,	0x20821022,
100 	0x0,	0x0,	0x0,	0x0,
101 	0x0,	0x0,	0x0,	0x0,
102 	0x0,	0x0,	0x0,	0x0,
103 	0x0,	0x0,	0x0,	0x0,
107 static const uint32_t isa_hdr[] = {  /* dev f function 0 - devfn = 78 */
108 	0xfffffff9, 0xffffff01, 0xffffffc1, 0xffffffe1,
109 	0xffffff81, 0xffffffc1, 0x0, 0x0,
111 	0x20901022, 0x2a00049, 0x6010003, 0x802000,
112 	0x18b1,	0x1001,	0x1801,	0x1881,	/* SMB-8   GPIO-256 MFGPT-64  IRQ-32 */
113 	0x1401,	0x1841,	0x0,	0x20901022,		/* PMS-128 ACPI-64 */
114 	0x0,	0x0,	0x0,	0x0,
115 	0x0,	0x0,	0x0,	0x0,
116 	0x0,	0x0,	0x0,	0xaa5b,			/* IRQ steering */
117 	0x0,	0x0,	0x0,	0x0,
121 	0xffffff81, 0x0, 0x0,	0x0,
122 	0x0,	0x0,	0x0,	0x0,
124 	0x20931022, 0x2a00041, 0x4010001, 0x0,
125 	0x1481,	0x0,	0x0,	0x0,			/* I/O BAR-128 */
126 	0x0,	0x0,	0x0,	0x20931022,
127 	0x0,	0x0,	0x0,	0x205,			/* IntB, IRQ5 */
128 	0x0,	0x0,	0x0,	0x0,
129 	0x0,	0x0,	0x0,	0x0,
130 	0x0,	0x0,	0x0,	0x0,
134 	0xfffff000, 0x0, 0x0,	0x0,
135 	0x0,	0x0,	0x0,	0x0,
137 	0x20941022, 0x2300006, 0xc031002, 0x0,
138 	0xfe01a000, 0x0, 0x0,	0x0,			/* MEMBAR-1000 */
139 	0x0,	0x0,	0x0,	0x20941022,
140 	0x0,	0x40,	0x0,	0x40a,			/* CapPtr INT-D, IRQA */
141 	0xc8020001, 0x0, 0x0,	0x0,	/* Capabilities - 40 is R/O,
143 	0x0,	0x0,	0x0,	0x0,
144 	0x0,	0x0,	0x0,	0x0,
148 	0xfffff000, 0x0, 0x0,	0x0,
149 	0x0,	0x0,	0x0,	0x0,
151 	0x20951022, 0x2300006, 0xc032002, 0x0,
152 	0xfe01b000, 0x0, 0x0,	0x0,			/* MEMBAR-1000 */
153 	0x0,	0x0,	0x0,	0x20951022,
154 	0x0,	0x40,	0x0,	0x40a,			/* CapPtr INT-D, IRQA */
155 	0xc8020001, 0x0, 0x0,	0x0,	/* Capabilities - 40 is R/O, 44 is
157 	0x01000001, 0x0, 0x0,	0x0,	/* EECP - see EHCI spec section 2.1.7 */
158 	0x2020,	0x0,	0x0,	0x0,	/* (EHCI page 8) 60 SBRN (R/O),
162 static uint32_t ff_loc = ~0;
164 static int bar_probing;		/* Set after a write of ~0 to a BAR */
167 #define NB_SLOT 0x1	/* Northbridge - GX chip - Device 1 */
168 #define SB_SLOT 0xf	/* Southbridge - CS5536 chip - Device F */
182 	 * 0x20 bytes of size masks, followed by 0x70 bytes of header data.  in hdr_addr()
184 	 * to access the header data, so we add 0x20 to the reg offset,  in hdr_addr()
187 	 * the BAR, so we subtract 0x10 (the config header offset for  in hdr_addr()
191 	addr = (uint32_t)hdr + reg + (bar_probing ? -0x10 : 0x20);  in hdr_addr()
193 	bar_probing = 0;  in hdr_addr()
209 	 * No device has config registers past 0x70, so we save table space  in pci_olpc_read()
212 	if (reg >= 0x70)  in pci_olpc_read()
216 		case  0x8:  in pci_olpc_read()
219 		case  0x9:  in pci_olpc_read()
222 		case  0xa:  in pci_olpc_read()
225 		case 0x78:  in pci_olpc_read()
228 		case 0x7b:  in pci_olpc_read()
231 		case 0x7c:  in pci_olpc_read()
234 		case 0x7d:  in pci_olpc_read()
256 	return 0;  in pci_olpc_read()
272 	 * (i.e. writing ~0 to a BAR), we remember it and arrange to return  in pci_olpc_write()
278 	if ((reg >= 0x10) && (reg < 0x2c)) {  in pci_olpc_write()
280 		if (value == ~0)  in pci_olpc_write()
289 				(reg != PCI_CACHE_LINE_SIZE) && (reg != 0x44))  in pci_olpc_write()
294 	return 0;  in pci_olpc_write()
307 	return 0;  in pci_olpc_init()