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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dgk104.c29 return (nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x4) == 0x4 ? 2 : 1; in gk104_pcie_version_supported()
40 nvkm_mask(device, 0x8c1c0, 0x30000, 0x10000); in gk104_pcie_set_cap_speed()
44 nvkm_mask(device, 0x8c1c0, 0x30000, 0x20000); in gk104_pcie_set_cap_speed()
48 nvkm_mask(device, 0x8c1c0, 0x30000, 0x30000); in gk104_pcie_set_cap_speed()
58 if (speed == 0) in gk104_pcie_cap_speed()
62 int speed2 = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x30000; in gk104_pcie_cap_speed()
64 case 0x00000: in gk104_pcie_cap_speed()
65 case 0x10000: in gk104_pcie_cap_speed()
67 case 0x20000: in gk104_pcie_cap_speed()
69 case 0x30000: in gk104_pcie_cap_speed()
[all …]
Dg84.c39 return (nvkm_rd32(device, 0x00154c) & 0x1) + 1; in g84_pcie_version()
46 nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0)); in g84_pcie_set_version()
53 nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0); in g84_pcie_set_cap_speed()
59 u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000; in g84_pcie_cur_speed()
61 case 0x30000: in g84_pcie_cur_speed()
63 case 0x20000: in g84_pcie_cur_speed()
65 case 0x10000: in g84_pcie_cur_speed()
74 u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300; in g84_pcie_max_speed()
75 if (reg_v == 0x2200) in g84_pcie_max_speed()
86 mask_value = 0x20; in g84_pcie_set_link_speed()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/apple/
Dt6002.dtsi70 reg = <0x0 0x800>;
72 cpu-release-addr = <0 0>; /* To be filled by loader */
74 i-cache-size = <0x20000>;
75 d-cache-size = <0x10000>;
84 reg = <0x0 0x801>;
86 cpu-release-addr = <0 0>; /* To be filled by loader */
88 i-cache-size = <0x20000>;
89 d-cache-size = <0x10000>;
98 reg = <0x0 0x10900>;
100 cpu-release-addr = <0 0>; /* To be filled by loader */
[all …]
Dt600x-common.dtsi16 #size-cells = <0>;
59 cpu_e00: cpu@0 {
62 reg = <0x0 0x0>;
64 cpu-release-addr = <0 0>; /* To be filled by loader */
66 i-cache-size = <0x20000>;
67 d-cache-size = <0x10000>;
76 reg = <0x0 0x1>;
78 cpu-release-addr = <0 0>; /* To be filled by loader */
80 i-cache-size = <0x20000>;
81 d-cache-size = <0x10000>;
[all …]
/linux-6.12.1/drivers/accel/habanalabs/include/goya/asic_reg/
Dcpu_ca53_cfg_masks.h23 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0
24 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3
26 #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30
28 #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300
30 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000
33 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0
34 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF
37 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0
38 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF
41 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dpq3-sec4.4-0.dtsi2 * PQ3 Sec/Crypto 4.4 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
40 ranges = <0x0 0x30000 0x10000>;
41 reg = <0x30000 0x10000>;
42 interrupts = <58 2 0 0>;
45 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>;
47 interrupts = <45 2 0 0>;
51 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
52 reg = <0x2000 0x1000>;
[all …]
Dpq3-sec2.1-0.dtsi2 * PQ3 Sec/Crypto 2.1 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec2.1", "fsl,sec2.0";
37 reg = <0x30000 0x10000>;
38 interrupts = <45 2 0 0>;
41 fsl,exec-units-mask = <0xfe>;
42 fsl,descriptor-types-mask = <0x12b0ebf>;
Dpq3-sec3.3-0.dtsi2 * PQ3 Sec/Crypto 3.3 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.3", "fsl,sec3.1", "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0x97c>;
44 fsl,descriptor-types-mask = <0x3a30abf>;
Dpq3-sec3.1-0.dtsi2 * PQ3 Sec/Crypto 3.1 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.1", "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0xbfe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
Dpq3-sec3.0-0.dtsi2 * PQ3 Sec/Crypto 3.0 device tree stub [ controller @ offset 0x30000 ]
36 compatible = "fsl,sec3.0",
38 "fsl,sec2.0";
39 reg = <0x30000 0x10000>;
40 interrupts = <45 2 0 0 58 2 0 0>;
43 fsl,exec-units-mask = <0x9fe>;
44 fsl,descriptor-types-mask = <0x3ab0ebf>;
/linux-6.12.1/arch/s390/include/asm/
Dspinlock.h50 return lock.lock == 0; in arch_spin_value_unlocked()
55 return READ_ONCE(lp->lock) != 0; in arch_spin_is_locked()
61 return likely(__atomic_cmpxchg_bool(&lp->lock, 0, SPINLOCK_LOCKVAL)); in arch_spin_trylock_once()
82 ALTERNATIVE("nop", ".insn rre,0xb2fa0000,7,0", ALT_FACILITY(49)) /* NIAI 7 */ in arch_spin_unlock()
83 " sth %1,%0\n" in arch_spin_unlock()
85 : "d" (0) : "cc", "memory"); in arch_spin_unlock()
110 if (old & 0xffff0000) in arch_read_lock()
121 if (!__atomic_cmpxchg_bool(&rw->cnts, 0, 0x30000)) in arch_write_lock()
127 __atomic_add_barrier(-0x30000, &rw->cnts); in arch_write_unlock()
136 return (!(old & 0xffff0000) && in arch_read_trylock()
[all …]
/linux-6.12.1/arch/mips/boot/dts/ralink/
Drt2880_eval.dts10 memory@0 {
12 reg = <0x8000000 0x2000000>;
21 reg = <0x1f000000 0x400000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x3b0000>;
Drt3052_eval.dts10 memory@0 {
12 reg = <0x0 0x2000000>;
21 reg = <0x1f000000 0x800000>;
28 partition@0 {
30 reg = <0x0 0x30000>;
35 reg = <0x30000 0x10000>;
40 reg = <0x40000 0x10000>;
45 reg = <0x50000 0x7b0000>;
Dmt7621-gnubee-gb-pc1.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
57 flash@0 {
61 reg = <0>;
65 partition@0 {
67 reg = <0x0 0x30000>;
73 reg = <0x30000 0x10000>;
79 reg = <0x40000 0x10000>;
85 reg = <0x50000 0x1fb0000>;
[all …]
Dmt7621-gnubee-gb-pc2.dts13 memory@0 {
15 reg = <0x00000000 0x1c000000>,
16 <0x20000000 0x04000000>;
77 flash@0 {
81 reg = <0>;
85 partition@0 {
87 reg = <0x0 0x30000>;
93 reg = <0x30000 0x10000>;
99 reg = <0x40000 0x10000>;
105 reg = <0x50000 0x1fb0000>;
[all …]
/linux-6.12.1/drivers/clk/imx/
Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Dkirkwood-dir665.dts18 reg = <0x00000000 0x8000000>; /* 128 MB */
28 pinctrl-0 =< &pmx_led_usb
81 flash@0 {
86 reg = <0>;
88 partition@0 {
90 reg = <0x0 0x30000>;
96 reg = <0x30000 0x10000>;
102 reg = <0x40000 0x180000>;
107 reg = <0x1c0000 0xe00000>;
112 reg = <0xfc0000 0x10000>;
[all …]
Dorion5x-linkstation.dtsi55 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
56 <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
57 <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>;
67 #size-cells = <0>;
68 pinctrl-0 = <&pmx_power_usb &pmx_power_hdd>;
109 flash@0 {
111 reg = <0 0x40000>;
119 header@0 {
120 reg = <0 0x30000>;
125 reg = <0x30000 0xF000>;
[all …]
/linux-6.12.1/arch/arm/mach-dove/
Ddove.h14 * e0000000 @runtime 128M PCIe-0 Memory space
18 * f2000000 fee00000 1M PCIe-0 I/O space
22 #define DOVE_CESA_PHYS_BASE 0xc8000000
23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000
32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000
35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,sc7280-lpasscorecc.yaml136 reg = <0x3300000 0x30000>,
137 <0x32a9000 0x1000>;
154 reg = <0x3c00000 0x28>;
168 reg = <0x3900000 0x50000>;
183 reg = <0x3380000 0x30000>;
Dqcom,qcs404-turingcc.yaml42 reg = <0x00800000 0x30000>;
/linux-6.12.1/drivers/accel/habanalabs/include/gaudi2/asic_reg/
Drot0_masks.h24 #define ROT0_KMD_MODE_EN_SHIFT 0
25 #define ROT0_KMD_MODE_EN_MASK 0x1
28 #define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0
29 #define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1
32 #define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0
33 #define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF
36 #define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0
37 #define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF
40 #define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0
41 #define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/abi/
Dgsc_proxy_commands_abi.h18 * Bits 0-7: type of the proxy message (see enum xe_gsc_proxy_type)
23 #define GSC_PROXY_TYPE GENMASK(7, 0)
28 #define GSC_PROXY_ADDRESSING_KMD 0x10000
29 #define GSC_PROXY_ADDRESSING_GSC 0x20000
30 #define GSC_PROXY_ADDRESSING_CSME 0x30000
37 GSC_PROXY_MSG_TYPE_PROXY_INVALID = 0,
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dmediatek-vpu.txt25 reg = <0 0x10020000 0 0x30000>,
26 <0 0x10050000 0 0x100>;
/linux-6.12.1/Documentation/devicetree/bindings/display/msm/
Dgmu.yaml24 - pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
298 reg = <0x506a000 0x30000>,
299 <0xb280000 0x10000>,
300 <0xb480000 0x10000>;
323 reg = <0x0596a000 0x30000>;

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