Lines Matching +full:0 +full:x30000

24 #define ROT0_KMD_MODE_EN_SHIFT 0
25 #define ROT0_KMD_MODE_EN_MASK 0x1
28 #define ROT0_CPL_QUEUE_EN_Q_EN_SHIFT 0
29 #define ROT0_CPL_QUEUE_EN_Q_EN_MASK 0x1
32 #define ROT0_CPL_QUEUE_ADDR_L_VAL_SHIFT 0
33 #define ROT0_CPL_QUEUE_ADDR_L_VAL_MASK 0xFFFFFFFF
36 #define ROT0_CPL_QUEUE_ADDR_H_VAL_SHIFT 0
37 #define ROT0_CPL_QUEUE_ADDR_H_VAL_MASK 0xFFFFFFFF
40 #define ROT0_CPL_QUEUE_DATA_VAL_SHIFT 0
41 #define ROT0_CPL_QUEUE_DATA_VAL_MASK 0xFFFFFFFF
44 #define ROT0_CPL_QUEUE_AWUSER_VAL_SHIFT 0
45 #define ROT0_CPL_QUEUE_AWUSER_VAL_MASK 0xFFFFFFFF
48 #define ROT0_CPL_QUEUE_AXI_CACHE_SHIFT 0
49 #define ROT0_CPL_QUEUE_AXI_CACHE_MASK 0xF
51 #define ROT0_CPL_QUEUE_AXI_PROT_MASK 0x70
54 #define ROT0_CPL_MSG_THRESHOLD_VAL_SHIFT 0
55 #define ROT0_CPL_MSG_THRESHOLD_VAL_MASK 0x3F
58 #define ROT0_CPL_MSG_AXI_CACHE_SHIFT 0
59 #define ROT0_CPL_MSG_AXI_CACHE_MASK 0xF
61 #define ROT0_CPL_MSG_AXI_PROT_MASK 0x70
64 #define ROT0_AXI_WB_CACHE_SHIFT 0
65 #define ROT0_AXI_WB_CACHE_MASK 0xF
67 #define ROT0_AXI_WB_PROT_MASK 0x70
70 #define ROT0_ERR_CFG_STOP_ON_ERR_SHIFT 0
71 #define ROT0_ERR_CFG_STOP_ON_ERR_MASK 0x1
74 #define ROT0_ERR_STATUS_ROT_HBW_RD_SHIFT 0
75 #define ROT0_ERR_STATUS_ROT_HBW_RD_MASK 0x1
77 #define ROT0_ERR_STATUS_ROT_HBW_WR_MASK 0x2
79 #define ROT0_ERR_STATUS_QMAN_HBW_RD_MASK 0x4
81 #define ROT0_ERR_STATUS_QMAN_HBW_WR_MASK 0x8
83 #define ROT0_ERR_STATUS_ROT_LBW_WR_MASK 0x10
86 #define ROT0_WBC_MAX_OUTSTANDING_VAL_SHIFT 0
87 #define ROT0_WBC_MAX_OUTSTANDING_VAL_MASK 0xFFFF
90 #define ROT0_WBC_RL_SATURATION_SHIFT 0
91 #define ROT0_WBC_RL_SATURATION_MASK 0xFF
93 #define ROT0_WBC_RL_TIMEOUT_MASK 0xFF00
95 #define ROT0_WBC_RL_RST_TOKEN_MASK 0xFF0000
97 #define ROT0_WBC_RL_RATE_LIMITER_EN_MASK 0x1000000
100 #define ROT0_WBC_INFLIGHTS_VAL_SHIFT 0
101 #define ROT0_WBC_INFLIGHTS_VAL_MASK 0xFFFF
104 #define ROT0_WBC_INFO_EMPTY_SHIFT 0
105 #define ROT0_WBC_INFO_EMPTY_MASK 0x1
107 #define ROT0_WBC_INFO_AXI_IDLE_MASK 0x2
110 #define ROT0_WBC_MON_CNT_SHIFT 0
111 #define ROT0_WBC_MON_CNT_MASK 0x1
113 #define ROT0_WBC_MON_TS_MASK 0x300
115 #define ROT0_WBC_MON_CONTEXT_ID_MASK 0xFFFF0000
118 #define ROT0_RSB_CAM_MAX_SIZE_DATA_SHIFT 0
119 #define ROT0_RSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF
121 #define ROT0_RSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000
124 #define ROT0_RSB_CFG_CACHE_DISABLE_SHIFT 0
125 #define ROT0_RSB_CFG_CACHE_DISABLE_MASK 0x1
127 #define ROT0_RSB_CFG_ENABLE_CGATE_MASK 0x2
130 #define ROT0_RSB_MAX_OS_VAL_SHIFT 0
131 #define ROT0_RSB_MAX_OS_VAL_MASK 0xFFFF
134 #define ROT0_RSB_RL_SATURATION_SHIFT 0
135 #define ROT0_RSB_RL_SATURATION_MASK 0xFF
137 #define ROT0_RSB_RL_TIMEOUT_MASK 0xFF00
139 #define ROT0_RSB_RL_RST_TOKEN_MASK 0xFF0000
141 #define ROT0_RSB_RL_RATE_LIMITER_EN_MASK 0x1000000
144 #define ROT0_RSB_INFLIGHTS_VAL_SHIFT 0
145 #define ROT0_RSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF
148 #define ROT0_RSB_OCCUPANCY_VAL_SHIFT 0
149 #define ROT0_RSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF
152 #define ROT0_RSB_INFO_EMPTY_SHIFT 0
153 #define ROT0_RSB_INFO_EMPTY_MASK 0x1
155 #define ROT0_RSB_INFO_AXI_IDLE_MASK 0x2
158 #define ROT0_RSB_MON_CNT_SHIFT 0
159 #define ROT0_RSB_MON_CNT_MASK 0x1FFF
161 #define ROT0_RSB_MON_TS_MASK 0x30000
164 #define ROT0_RSB_MON_CONTEXT_ID_VAL_SHIFT 0
165 #define ROT0_RSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF
168 #define ROT0_MSS_HALT_VAL_SHIFT 0
169 #define ROT0_MSS_HALT_VAL_MASK 0x7
172 #define ROT0_MSS_SEI_STATUS_I0_SHIFT 0
173 #define ROT0_MSS_SEI_STATUS_I0_MASK 0x1
175 #define ROT0_MSS_SEI_STATUS_I1_MASK 0x2
177 #define ROT0_MSS_SEI_STATUS_I2_MASK 0x4
179 #define ROT0_MSS_SEI_STATUS_I3_MASK 0x8
181 #define ROT0_MSS_SEI_STATUS_I4_MASK 0x10
183 #define ROT0_MSS_SEI_STATUS_I5_MASK 0x20
185 #define ROT0_MSS_SEI_STATUS_I6_MASK 0x40
187 #define ROT0_MSS_SEI_STATUS_I7_MASK 0x80
189 #define ROT0_MSS_SEI_STATUS_I8_MASK 0x100
191 #define ROT0_MSS_SEI_STATUS_I9_MASK 0x200
193 #define ROT0_MSS_SEI_STATUS_I10_MASK 0x400
195 #define ROT0_MSS_SEI_STATUS_I11_MASK 0x800
197 #define ROT0_MSS_SEI_STATUS_I12_MASK 0x1000
199 #define ROT0_MSS_SEI_STATUS_I13_MASK 0x2000
201 #define ROT0_MSS_SEI_STATUS_I14_MASK 0x4000
203 #define ROT0_MSS_SEI_STATUS_I15_MASK 0x8000
205 #define ROT0_MSS_SEI_STATUS_I16_MASK 0x10000
207 #define ROT0_MSS_SEI_STATUS_I17_MASK 0x20000
209 #define ROT0_MSS_SEI_STATUS_I18_MASK 0x40000
211 #define ROT0_MSS_SEI_STATUS_I19_MASK 0x80000
213 #define ROT0_MSS_SEI_STATUS_I20_MASK 0x100000
215 #define ROT0_MSS_SEI_STATUS_I21_MASK 0x200000
218 #define ROT0_MSS_SEI_MASK_VAL_SHIFT 0
219 #define ROT0_MSS_SEI_MASK_VAL_MASK 0x3FFFFF
222 #define ROT0_MSS_SPI_STATUS_I0_SHIFT 0
223 #define ROT0_MSS_SPI_STATUS_I0_MASK 0x1
225 #define ROT0_MSS_SPI_STATUS_I1_MASK 0x2
227 #define ROT0_MSS_SPI_STATUS_I2_MASK 0x4
229 #define ROT0_MSS_SPI_STATUS_I3_MASK 0x8
231 #define ROT0_MSS_SPI_STATUS_I4_MASK 0x10
233 #define ROT0_MSS_SPI_STATUS_I5_MASK 0x20
235 #define ROT0_MSS_SPI_STATUS_I6_MASK 0x40
237 #define ROT0_MSS_SPI_STATUS_I7_MASK 0x80
240 #define ROT0_MSS_SPI_MASK_VAL_SHIFT 0
241 #define ROT0_MSS_SPI_MASK_VAL_MASK 0xFF
244 #define ROT0_DISABLE_PAD_CALC_VAL_SHIFT 0
245 #define ROT0_DISABLE_PAD_CALC_VAL_MASK 0x3
248 #define ROT0_QMAN_CFG_FORCE_STOP_SHIFT 0
249 #define ROT0_QMAN_CFG_FORCE_STOP_MASK 0x1
252 #define ROT0_CLK_EN_LBW_CFG_DIS_SHIFT 0
253 #define ROT0_CLK_EN_LBW_CFG_DIS_MASK 0x1
255 #define ROT0_CLK_EN_DBG_CFG_DIS_MASK 0x10
257 #define ROT0_CLK_EN_SB_EMPTY_MASK_MASK 0x20
260 #define ROT0_MRSB_CAM_MAX_SIZE_DATA_SHIFT 0
261 #define ROT0_MRSB_CAM_MAX_SIZE_DATA_MASK 0xFFFF
263 #define ROT0_MRSB_CAM_MAX_SIZE_MD_MASK 0xFFFF0000
266 #define ROT0_MRSB_CFG_CACHE_DISABLE_SHIFT 0
267 #define ROT0_MRSB_CFG_CACHE_DISABLE_MASK 0x1
269 #define ROT0_MRSB_CFG_ENABLE_CGATE_MASK 0x2
272 #define ROT0_MRSB_MAX_OS_VAL_SHIFT 0
273 #define ROT0_MRSB_MAX_OS_VAL_MASK 0xFFFF
276 #define ROT0_MRSB_RL_SATURATION_SHIFT 0
277 #define ROT0_MRSB_RL_SATURATION_MASK 0xFF
279 #define ROT0_MRSB_RL_TIMEOUT_MASK 0xFF00
281 #define ROT0_MRSB_RL_RST_TOKEN_MASK 0xFF0000
283 #define ROT0_MRSB_RL_RATE_LIMITER_EN_MASK 0x1000000
286 #define ROT0_MRSB_INFLIGHTS_VAL_SHIFT 0
287 #define ROT0_MRSB_INFLIGHTS_VAL_MASK 0xFFFFFFFF
290 #define ROT0_MRSB_OCCUPANCY_VAL_SHIFT 0
291 #define ROT0_MRSB_OCCUPANCY_VAL_MASK 0xFFFFFFFF
294 #define ROT0_MRSB_INFO_EMPTY_SHIFT 0
295 #define ROT0_MRSB_INFO_EMPTY_MASK 0x1
297 #define ROT0_MRSB_INFO_AXI_IDLE_MASK 0x2
300 #define ROT0_MRSB_MON_CNT_SHIFT 0
301 #define ROT0_MRSB_MON_CNT_MASK 0x1FFF
303 #define ROT0_MRSB_MON_TS_MASK 0x30000
306 #define ROT0_MRSB_MON_CONTEXT_ID_VAL_SHIFT 0
307 #define ROT0_MRSB_MON_CONTEXT_ID_VAL_MASK 0xFFFFFFFF
310 #define ROT0_MSS_STS_IS_HALT_SHIFT 0
311 #define ROT0_MSS_STS_IS_HALT_MASK 0x1