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/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dpq3-etsec1-2.dtsi2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
42 reg = <0x26000 0x1000>;
43 ranges = <0x0 0x26000 0x1000>;
46 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
51 #size-cells = <0>;
53 reg = <0x26520 0x20>;
Dpq3-etsec2-2.dtsi2 * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
37 #size-cells = <0>;
39 reg = <0x26000 0x1000 0xb1030 0x4>;
48 fsl,num_rx_queues = <0x8>;
49 fsl,num_tx_queues = <0x8>;
57 reg = <0xb2000 0x1000>;
58 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
/linux-6.12.1/arch/arm/boot/dts/ti/omap/
Dam57-pruss.dtsi11 reg = <0x4b226000 0x4>,
12 <0x4b226004 0x4>;
23 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
27 ranges = <0x00000000 0x4b200000 0x80000>;
29 pruss1: pruss@0 {
31 reg = <0x0 0x80000>;
36 pruss1_mem: memories@0 {
37 reg = <0x0 0x2000>,
38 <0x2000 0x2000>,
39 <0x10000 0x8000>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
161 const: 0
175 const: 0
209 const: 0
317 "^(pru|rtu|txpru)@[0-9a-f]+$":
370 pruss: pruss@0 {
372 reg = <0x0 0x80000>;
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
Dxpedite5200.dts30 #size-cells = <0>;
32 PowerPC,8548@0 {
34 reg = <0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
45 reg = <0x0 0x0>; // Filled in by U-Boot
52 ranges = <0x0 0xef000000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
58 reg = <0x0 0x1000>;
[all …]
Dtqm8548-bigflash.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xa0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
Dtqm8548.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
Dxpedite5200_xmon.dts18 boot-bank = <0x0>;
34 #size-cells = <0>;
36 PowerPC,8548@0 {
38 reg = <0>;
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
49 reg = <0x0 0x0>; // Filled in by boot loader
56 ranges = <0x0 0xef000000 0x100000>;
57 bus-frequency = <0>;
60 ecm-law@0 {
[all …]
Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/catalog/
Ddpu_4_1_sdm670.h13 .base = 0x0, .len = 0x45c,
16 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
17 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
18 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
19 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
20 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
27 .base = 0x4000, .len = 0x1c8,
30 .xin_id = 0,
35 .base = 0x6000, .len = 0x1c8,
43 .base = 0x24000, .len = 0x1c8,
[all …]
Ddpu_3_3_sdm630.h11 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x458,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
31 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
38 .base = 0x1000, .len = 0x94,
43 .base = 0x1200, .len = 0x94,
47 .base = 0x1400, .len = 0x94,
[all …]
Ddpu_6_2_sc7180.h12 .max_mixer_blendstages = 0x9,
21 .base = 0x0, .len = 0x494,
23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 .base = 0x1000, .len = 0x1dc,
39 .base = 0x1200, .len = 0x1dc,
44 .base = 0x1400, .len = 0x1dc,
[all …]
Ddpu_6_4_sm6350.h13 .max_mixer_blendstages = 0x7,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
27 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
28 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
29 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
30 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
37 .base = 0x1000, .len = 0x1dc,
42 .base = 0x1200, .len = 0x1dc,
[all …]
Ddpu_5_4_sm6125.h13 .max_mixer_blendstages = 0x6,
24 .base = 0x0, .len = 0x45c,
25 .features = 0,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
37 .base = 0x1000, .len = 0x1e0,
42 .base = 0x1200, .len = 0x1e0,
47 .base = 0x1400, .len = 0x1e0,
[all …]
Ddpu_7_2_sc7280.h12 .max_mixer_blendstages = 0x7,
21 .base = 0x0, .len = 0x2014,
23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 },
34 .base = 0x15000, .len = 0x1e8,
39 .base = 0x16000, .len = 0x1e8,
44 .base = 0x17000, .len = 0x1e8,
[all …]
Ddpu_3_2_sdm660.h11 .max_mixer_blendstages = 0x7,
24 .base = 0x0, .len = 0x458,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
32 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 },
39 .base = 0x1000, .len = 0x94,
44 .base = 0x1200, .len = 0x94,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dqcom,ssc-block-bus.yaml125 reg = <0x10ac008 0x4>, <0x10ac010 0x4>;
142 qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
/linux-6.12.1/arch/arm/mach-imx/
Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
/linux-6.12.1/sound/pci/au88x0/
Dau8810.h11 #define NR_ADB 0x10
12 #define NR_WT 0x00
13 #define NR_SRC 0x10
14 #define NR_A3D 0x10
15 #define NR_MIXIN 0x20
16 #define NR_MIXOUT 0x10
20 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
21 #define POS_MASK 0x00000fff
22 #define POS_SHIFT 0x0
23 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
Dau8830.h18 #define NR_ADB 0x20
19 #define NR_SRC 0x10
20 #define NR_A3D 0x10
21 #define NR_MIXIN 0x20
22 #define NR_MIXOUT 0x10
23 #define NR_WT 0x40
26 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
27 #define POS_MASK 0x00000fff
28 #define POS_SHIFT 0x0
29 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/regs/
Dxe_engine_regs.h18 #define RENDER_RING_BASE 0x02000
19 #define BSD_RING_BASE 0x1c0000
20 #define BSD2_RING_BASE 0x1c4000
21 #define BSD3_RING_BASE 0x1d0000
22 #define BSD4_RING_BASE 0x1d4000
23 #define XEHP_BSD5_RING_BASE 0x1e0000
24 #define XEHP_BSD6_RING_BASE 0x1e4000
25 #define XEHP_BSD7_RING_BASE 0x1f0000
26 #define XEHP_BSD8_RING_BASE 0x1f4000
27 #define VEBOX_RING_BASE 0x1c8000
[all …]

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