Lines Matching +full:0 +full:x26000
30 #size-cells = <0>;
32 PowerPC,8548@0 {
34 reg = <0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
45 reg = <0x0 0x0>; // Filled in by U-Boot
52 ranges = <0x0 0xef000000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
58 reg = <0x0 0x1000>;
64 reg = <0x1000 0x1000>;
71 reg = <0x2000 0x1000>;
78 reg = <0x20000 0x1000>;
80 cache-size = <0x80000>; // L2, 512K
88 #size-cells = <0>;
89 cell-index = <0>;
91 reg = <0x3000 0x100>;
98 * 0: BRD_CFG0 (1: P14 IO present)
109 reg = <0x18>;
112 polarity = <0x00>;
118 reg = <0x19>;
121 polarity = <0x00>;
126 reg = <0x50>;
132 reg = <0x68>;
137 reg = <0x34>;
144 #size-cells = <0>;
147 reg = <0x3100 0x100>;
157 reg = <0x21300 0x4>;
158 ranges = <0x0 0x21100 0x200>;
159 cell-index = <0>;
160 dma-channel@0 {
163 reg = <0x0 0x80>;
164 cell-index = <0>;
171 reg = <0x80 0x80>;
179 reg = <0x100 0x80>;
187 reg = <0x180 0x80>;
194 /* eTSEC1: Front panel port 0 */
198 cell-index = <0>;
202 reg = <0x24000 0x1000>;
203 ranges = <0x0 0x24000 0x1000>;
212 #size-cells = <0>;
214 reg = <0x520 0x20>;
219 reg = <0x1>;
224 reg = <0x2>;
229 reg = <0x3>;
234 reg = <0x4>;
237 reg = <0x11>;
251 reg = <0x25000 0x1000>;
252 ranges = <0x0 0x25000 0x1000>;
261 #size-cells = <0>;
263 reg = <0x520 0x20>;
266 reg = <0x11>;
280 reg = <0x26000 0x1000>;
281 ranges = <0x0 0x26000 0x1000>;
290 #size-cells = <0>;
292 reg = <0x520 0x20>;
295 reg = <0x11>;
309 reg = <0x27000 0x1000>;
310 ranges = <0x0 0x27000 0x1000>;
319 #size-cells = <0>;
321 reg = <0x520 0x20>;
324 reg = <0x11>;
331 cell-index = <0>;
334 reg = <0x4500 0x100>;
335 clock-frequency = <0>;
345 reg = <0x4600 0x100>;
346 clock-frequency = <0>;
354 reg = <0xe0000 0x1000>;
360 #address-cells = <0>;
362 reg = <0x40000 0x40000>;
373 reg = <0xef005000 0x100>; // BRx, ORx, etc.
378 0 0x0 0xfc000000 0x04000000 // NOR boot flash
379 1 0x0 0xf8000000 0x04000000 // NOR expansion flash
380 2 0x0 0xef800000 0x00010000 // NAND CE1
381 3 0x0 0xef840000 0x00010000 // NAND CE2
384 nor-boot@0,0 {
388 reg = <0 0x0 0x4000000>;
391 partition@0 {
393 reg = <0x00000000 0x180000>;
397 reg = <0x00180000 0x180000>;
401 reg = <0x00300000 0x3c80000>;
405 reg = <0x03f80000 0x80000>;
409 nor-alternate@1,0 {
413 reg = <1 0x0 0x4000000>;
416 partition@0 {
418 reg = <0x00000000 0x3f80000>;
422 reg = <0x03f80000 0x80000>;
426 nand@2,0 {
430 reg = <2 0x0 0x10000>;
431 cle-line = <0x8>; /* CLE tied to A3 */
432 ale-line = <0x10>; /* ALE tied to A4 */
435 partition@0 {
437 reg = <0 0x40000000>;
449 reg = <0xef008000 0x1000>;
451 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
454 0xe000 0 0 1 &mpic 2 1
455 0xe000 0 0 2 &mpic 3 1>;
459 bus-range = <0 0>;
460 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
461 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;