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/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-385-linksys-caiman.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
Darmada-385-linksys-cobra.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
Darmada-385-linksys-shelby.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Dti,rti-wdt.yaml42 PON_REASON_SOF_NUM(0xBBBBCCCC), PON_REASON_MAGIC_NUM(0xDDDDDDDD),
43 and PON_REASON_EOF_NUM(0xCCCCBBBB), are pre-stored at the first
48 specific memory address(0xa220000) should be set. More please
66 * starting from 0xa2200000 by RTI Watchdog Firmware, then make it
72 * reg = <0x00 0xa2200000 0x00 0x1000>;
81 reg = <0x2200000 0x100>;
/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dbrcm,bcm2835-gpio.txt17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
26 bits[3:0] trigger type and level flags:
66 are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
70 0: GPIO in
79 0: none
91 reg = <0x2200000 0xb4>;
/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dnvidia,tegra186-gpio.yaml122 - Bit 0 specifies polarity
123 - 0: Active-high (normal).
137 - Bits [3:0] indicate trigger type and level:
190 reg = <0x2200000 0x10000>,
191 <0x2210000 0x10000>;
192 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>,
193 <0 50 IRQ_TYPE_LEVEL_HIGH>,
194 <0 53 IRQ_TYPE_LEVEL_HIGH>,
195 <0 56 IRQ_TYPE_LEVEL_HIGH>,
196 <0 59 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux-6.12.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-sm-k26-revA.dts50 memory@0 {
52 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
61 reg = <0x0 0x7ff00000 0x0 0x100000>;
95 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
110 pwms = <&ttc0 2 40000 0>;
144 &qspi { /* MIO 0-5 - U143 */
146 spi_flash: flash@0 { /* MT25QU512A */
148 reg = <0>;
158 partition@0 {
160 reg = <0x0 0x80000>; /* 512KB */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dmsm8994-sony-xperia-kitakami.dtsi16 * We support MSM8994 v2 (0x20000) and v2.1 (0x20001).
17 * The V1 chip (0x0 and 0x10000) is significantly different
21 qcom,msm-id = <207 0x20000>, <207 0x20001>;
23 qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>;
25 qcom,board-id = <8 0>;
34 button-0 {
75 reg = <0 0x1fe00000 0 0x200000>;
76 console-size = <0x100000>;
77 record-size = <0x10000>;
78 ftrace-size = <0x10000>;
[all …]
Dsdm670-google-sargo.dts44 reg = <0 0x9c000000 0 (1080 * 2220 * 4)>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
71 pinctrl-0 = <&vol_up_pin>;
85 reg = <0 0x8b000000 0 0x9800000>;
90 reg = <0 0x94800000 0 0x500000>;
95 reg = <0 0x94d00000 0 0x100000>;
100 reg = <0 0x94e00000 0 0x800000>;
105 reg = <0 0x95600000 0 0x200000>;
110 reg = <0 0x95800000 0 0x2200000>;
[all …]
Dmsm8994.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
62 reg = <0x0 0x1>;
70 reg = <0x0 0x2>;
78 reg = <0x0 0x3>;
86 reg = <0x0 0x100>;
99 reg = <0x0 0x101>;
[all …]
/linux-6.12.1/arch/openrisc/kernel/
Dtraps.c61 if (i == 0) in print_data()
85 in_kernel = 0; in show_registers()
91 0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]); in show_registers()
160 pr_emerg("\n%s#: %04lx\n", str, err & 0xffff); in die()
176 pr_emerg("Unable to handle exception at EA =0x%x, vector 0x%x", in unhandled_exception()
208 pr_emerg("KERNEL: Illegal fpe exception 0x%.8lx\n", regs->pc); in do_fpe_trap()
218 pr_emerg("KERNEL: Illegal trap exception 0x%.8lx\n", regs->pc); in do_trap()
229 pr_emerg("KERNEL: Unaligned Access 0x%.8lx\n", address); in do_unaligned_access()
241 pr_emerg("KERNEL: Bus error (SIGBUS) 0x%.8lx\n", address); in do_bus_fault()
255 case 0x00: /* l.j */ in in_delay_slot()
[all …]
/linux-6.12.1/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hw.c15 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
19 #define CRB_BLK(off) ((off >> 20) & 0x3f)
20 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
21 #define CRB_WINDOW_2M (0x130060)
22 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
23 #define CRB_INDIRECT_2M (0x1e0000UL)
52 {{{0, 0, 0, 0} } }, /* 0: PCI */
53 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
54 {1, 0x0110000, 0x0120000, 0x130000},
55 {1, 0x0120000, 0x0122000, 0x124000},
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-j7200-main.dtsi10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
37 reg = <0x4080 0x20>;
39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
40 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
[all …]
Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
Dk3-j784s4-main.dtsi16 #clock-cells = <0>;
26 reg = <0x00 0x70000000 0x00 0x800000>;
29 ranges = <0x00 0x00 0x70000000 0x800000>;
31 atf-sram@0 {
32 reg = <0x00 0x20000>;
36 reg = <0x1f0000 0x10000>;
40 reg = <0x200000 0x200000>;
46 reg = <0x00 0x00100000 0x00 0x1c000>;
49 ranges = <0x00 0x00 0x00100000 0x1c000>;
53 reg = <0x4034 0x4>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
134 reg = <0x02900800 0x800>;
[all …]
Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]
/linux-6.12.1/drivers/net/ethernet/qlogic/netxen/
Dnetxen_nic_hw.c16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
18 #define MS_WIN(addr) (addr & 0x0ffc0000)
22 #define CRB_BLK(off) ((off >> 20) & 0x3f)
23 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
24 #define CRB_WINDOW_2M (0x130060)
25 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
26 #define CRB_INDIRECT_2M (0x1e0000UL)
57 {{{0, 0, 0, 0} } }, /* 0: PCI */
58 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
[all …]
/linux-6.12.1/drivers/scsi/qla2xxx/
Dqla_nx.c15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
25 #define BLOCK_PROTECT_BITS 0x0F
[all …]
/linux-6.12.1/drivers/scsi/qla4xxx/
Dql4_nx.c18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
[all …]