61 	if (i == 0)  in print_data()
85 		in_kernel = 0;  in show_registers()
91 		0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]);  in show_registers()
160 	pr_emerg("\n%s#: %04lx\n", str, err & 0xffff);  in die()
176 	pr_emerg("Unable to handle exception at EA =0x%x, vector 0x%x",  in unhandled_exception()
208 		pr_emerg("KERNEL: Illegal fpe exception 0x%.8lx\n", regs->pc);  in do_fpe_trap()
218 		pr_emerg("KERNEL: Illegal trap exception 0x%.8lx\n", regs->pc);  in do_trap()
229 		pr_emerg("KERNEL: Unaligned Access 0x%.8lx\n", address);  in do_unaligned_access()
241 		pr_emerg("KERNEL: Bus error (SIGBUS) 0x%.8lx\n", address);  in do_bus_fault()
255 	case 0x00: /* l.j */  in in_delay_slot()
256 	case 0x01: /* l.jal */  in in_delay_slot()
257 	case 0x03: /* l.bnf */  in in_delay_slot()
258 	case 0x04: /* l.bf */  in in_delay_slot()
259 	case 0x11: /* l.jr */  in in_delay_slot()
260 	case 0x12: /* l.jalr */  in in_delay_slot()
263 		return 0;  in in_delay_slot()
279 		displacement = sign_extend32(((jmp) & 0x3ffffff) << 2, 27);  in adjust_pc()
280 		rb = (jmp & 0x0000ffff) >> 11;  in adjust_pc()
284 		case 0x00: /* l.j */  in adjust_pc()
287 		case 0x01: /* l.jal */  in adjust_pc()
291 		case 0x03: /* l.bnf */  in adjust_pc()
297 		case 0x04: /* l.bf */  in adjust_pc()
303 		case 0x11: /* l.jr */  in adjust_pc()
306 		case 0x12: /* l.jalr */  in adjust_pc()
331 	ra = (insn >> 16) & 0x1f;  in simulate_lwa()
332 	rd = (insn >> 21) & 0x1f;  in simulate_lwa()
336 	if ((unsigned long)lwa_addr & 0x3) {  in simulate_lwa()
373 	ra = (insn >> 16) & 0x1f;  in simulate_swa()
374 	rb = (insn >> 11) & 0x1f;  in simulate_swa()
375 	imm = (short)(((insn & 0x2200000) >> 10) | (insn & 0x7ff));  in simulate_swa()
383 	if ((unsigned long)vaddr & 0x3) {  in simulate_swa()
403 	lwa_flag = 0;  in simulate_swa()
407 #define INSN_LWA	0x1b
408 #define INSN_SWA	0x33
435 		pr_emerg("KERNEL: Illegal instruction (SIGILL) 0x%.8lx\n",  in do_illegal_instruction()