Home
last modified time | relevance | path

Searched +full:0 +full:x2200 (Results 1 – 25 of 171) sorted by relevance

1234567

/linux-6.12.1/arch/arm/mach-mv78xx0/
Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/linux-6.12.1/sound/soc/codecs/
Drt715-sdca-sdw.c25 case 0x201a ... 0x2027: in rt715_sdca_readable_register()
26 case 0x2029 ... 0x202a: in rt715_sdca_readable_register()
27 case 0x202d ... 0x2034: in rt715_sdca_readable_register()
28 case 0x2200 ... 0x2204: in rt715_sdca_readable_register()
29 case 0x2206 ... 0x2212: in rt715_sdca_readable_register()
30 case 0x2230 ... 0x2239: in rt715_sdca_readable_register()
31 case 0x2f5b: in rt715_sdca_readable_register()
43 case 0x201b: in rt715_sdca_volatile_register()
44 case 0x201c: in rt715_sdca_volatile_register()
45 case 0x201d: in rt715_sdca_volatile_register()
[all …]
Drt722-sdca-sdw.h15 { 0x202d, 0x00 },
16 { 0x2f01, 0x00 },
17 { 0x2f02, 0x09 },
18 { 0x2f03, 0x00 },
19 { 0x2f04, 0x00 },
20 { 0x2f05, 0x0b },
21 { 0x2f06, 0x01 },
22 { 0x2f08, 0x00 },
23 { 0x2f09, 0x00 },
24 { 0x2f0a, 0x00 },
[all …]
Drt711-sdca-sdw.c22 case 0x201a ... 0x2027: in rt711_sdca_readable_register()
23 case 0x2029 ... 0x202a: in rt711_sdca_readable_register()
24 case 0x202d ... 0x2034: in rt711_sdca_readable_register()
25 case 0x2200 ... 0x2204: in rt711_sdca_readable_register()
26 case 0x2206 ... 0x2212: in rt711_sdca_readable_register()
27 case 0x2220 ... 0x2223: in rt711_sdca_readable_register()
28 case 0x2230 ... 0x2239: in rt711_sdca_readable_register()
29 case 0x2f01 ... 0x2f0f: in rt711_sdca_readable_register()
30 case 0x2f30 ... 0x2f36: in rt711_sdca_readable_register()
31 case 0x2f50 ... 0x2f5a: in rt711_sdca_readable_register()
[all …]
/linux-6.12.1/drivers/gpu/drm/radeon/reg_srcs/
Dr1001 r100 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
Dr2001 r200 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/media/
Dqcom,sm8250-camss.yaml113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
[all …]
/linux-6.12.1/arch/mips/include/asm/
Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux-6.12.1/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
/linux-6.12.1/drivers/net/wireless/rsi/
Drsi_sdio.h32 BUFFER_FULL = 0x0,
33 BUFFER_AVAILABLE = 0x2,
34 FIRMWARE_ASSERT_IND = 0x3,
35 MSDU_PACKET_PENDING = 0x4,
36 UNKNOWN_INT = 0XE
40 #define PKT_BUFF_SEMI_FULL 0
51 #define RSI_DEVICE_BUFFER_STATUS_REGISTER 0xf3
52 #define RSI_FN1_INT_REGISTER 0xf9
53 #define RSI_INT_ENABLE_REGISTER 0x04
54 #define RSI_INT_ENABLE_MASK 0xfc
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dt1024si-post.dtsi48 ranges = <0x0 0xf 0xfe140000 0x40000>;
49 reg = <0xf 0xfe140000 0 0x480>;
52 brg-frequency = <0>;
53 bus-frequency = <0>;
60 reg = <0x180000 1000>;
61 interrupts = <74 2 0 0>;
69 #address-cells = <0>;
71 reg = <0x80 0x80>;
72 interrupts = <95 2 0 0 94 2 0 0>; //high:79 low:78
77 reg = <0x2000 0x200>;
[all …]
/linux-6.12.1/drivers/ufs/host/
Dufs-mediatek.h15 #define MTK_MCQ_INVALID_IRQ 0xFFFF
18 #define EHS_EN BIT(0)
29 #define REG_UFS_XOUFS_CTRL 0x140
30 #define REG_UFS_REFCLK_CTRL 0x144
31 #define REG_UFS_MMIO_OPT_CTRL_0 0x160
32 #define REG_UFS_EXTREG 0x2100
33 #define REG_UFS_MPHYCTRL 0x2200
34 #define REG_UFS_MTK_IP_VER 0x2240
35 #define REG_UFS_REJECT_MON 0x22AC
36 #define REG_UFS_DEBUG_SEL 0x22C0
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dqcom,msm8996-qmp-pcie-phy.yaml57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x130>,
150 <0x1200 0x200>,
151 <0x1400 0x1dc>;
156 #clock-cells = <0>;
159 #phy-cells = <0>;
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Da4m072.dts27 ranges = <0 0xf0000000 0x0000c000>;
28 reg = <0xf0000000 0x00000100>;
29 bus-frequency = <0>; /* From boot loader */
30 system-frequency = <0>; /* From boot loader */
33 fsl,init-ext-48mhz-en = <0x0>;
34 fsl,init-fd-enable = <0x01>;
35 fsl,init-fd-counters = <0x3333>;
44 reg = <0x2000 0x100>;
45 interrupts = <2 1 0>;
50 reg = <0x2200 0x100>;
[all …]
Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dg84.c39 return (nvkm_rd32(device, 0x00154c) & 0x1) + 1; in g84_pcie_version()
46 nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0)); in g84_pcie_set_version()
53 nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0); in g84_pcie_set_cap_speed()
59 u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000; in g84_pcie_cur_speed()
61 case 0x30000: in g84_pcie_cur_speed()
63 case 0x20000: in g84_pcie_cur_speed()
65 case 0x10000: in g84_pcie_cur_speed()
74 u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300; in g84_pcie_max_speed()
75 if (reg_v == 0x2200) in g84_pcie_max_speed()
86 mask_value = 0x20; in g84_pcie_set_link_speed()
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/adreno/
Da2xx_gpu.c18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
/linux-6.12.1/lib/
Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/linux-6.12.1/drivers/regulator/
Dslg51000-regulator.h14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
[all …]
/linux-6.12.1/Documentation/translations/zh_CN/core-api/
Dprintk-formats.rst115 %pS versatile_init+0x0/0x110
117 %pSR versatile_init+0x9/0x110
119 %pB prev_fn_of_versatile_init+0x88/0x88
133 %pS versatile_init+0x0/0x110 [module_name]
134 %pSb versatile_init+0x0/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
135 %pSRb versatile_init+0x9/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
137 %pBb prev_fn_of_versatile_init+0x88/0x88 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
195 %pr [mem 0x60000000-0x6fffffff flags 0x2200] or
196 [mem 0x0000000060000000-0x000000006fffffff flags 0x2200]
197 %pR [mem 0x60000000-0x6fffffff pref] or
[all …]
/linux-6.12.1/drivers/mfd/
Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_offset.h25 // base address: 0x8000
26 …GRBM_CNTL 0x0000
27 …ne mmGRBM_CNTL_BASE_IDX 0
28 …GRBM_SKEW_CNTL 0x0001
29 …ne mmGRBM_SKEW_CNTL_BASE_IDX 0
30 …GRBM_STATUS2 0x0002
31 …ne mmGRBM_STATUS2_BASE_IDX 0
32 …GRBM_PWR_CNTL 0x0003
33 …ne mmGRBM_PWR_CNTL_BASE_IDX 0
34 …GRBM_STATUS 0x0004
[all …]
/linux-6.12.1/arch/mips/include/asm/octeon/
Dcvmx-ciu-defs.h13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
16 #define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17 #define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18 #define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19 #define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20 #define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21 #define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22 #define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23 #define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24 #define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
[all …]
/linux-6.12.1/drivers/media/radio/si4713/
Dsi4713.h25 #define SI4713_PRODUCT_NUMBER 0x0D
41 #define SI4713_PWUP_FUNC_TX 0x02
42 #define SI4713_PWUP_FUNC_PATCH 0x0F
43 #define SI4713_PWUP_OPMOD_ANALOG 0x50
44 #define SI4713_PWUP_OPMOD_DIGITAL 0x0F
47 #define SI4713_CMD_POWER_UP 0x01
50 #define SI4713_CMD_GET_REV 0x10
53 #define SI4713_CMD_POWER_DOWN 0x11
57 #define SI4713_CMD_SET_PROPERTY 0x12
61 #define SI4713_CMD_GET_PROPERTY 0x13
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s23 ctx_dma_query: .b32 0
24 ctx_dma_src: .b32 0
25 ctx_dma_dst: .b32 0
27 ctx_query_address_high: .b32 0
28 ctx_query_address_low: .b32 0
29 ctx_query_counter: .b32 0
30 ctx_cond_address_high: .b32 0
31 ctx_cond_address_low: .b32 0
32 ctx_cond_off: .b32 0
33 ctx_src_address_high: .b32 0
[all …]

1234567