sec/fuc/g98.fuc0s

23 ctx_dma_query:		.b32 0
24 ctx_dma_src:		.b32 0
25 ctx_dma_dst:		.b32 0
27 ctx_query_address_high:	.b32 0
28 ctx_query_address_low:	.b32 0
29 ctx_query_counter:	.b32 0
30 ctx_cond_address_high:	.b32 0
31 ctx_cond_address_low:	.b32 0
32 ctx_cond_off:		.b32 0
33 ctx_src_address_high:	.b32 0
34 ctx_src_address_low:	.b32 0
35 ctx_dst_address_high:	.b32 0
36 ctx_dst_address_low:	.b32 0
37 ctx_mode:		.b32 0
42 .align 0x80
48 .b32 #ctx_query_address_high + 0x20000 ~0xff
49 .b32 #ctx_query_address_low + 0x20000 ~0xfffffff0
50 .b32 #ctx_query_counter + 0x20000 ~0xffffffff
51 .b32 #cmd_query_get + 0x00000 ~1
52 .b32 #ctx_cond_address_high + 0x20000 ~0xff
53 .b32 #ctx_cond_address_low + 0x20000 ~0xfffffff0
54 .b32 #cmd_cond_mode + 0x00000 ~7
55 .b32 #cmd_wrcache_flush + 0x00000 ~0
56 .equ #common_cmd_max 0x88
61 .b32 #ctx_key + 0x0 + 0x20000 ~0xffffffff
62 .b32 #ctx_key + 0x4 + 0x20000 ~0xffffffff
63 .b32 #ctx_key + 0x8 + 0x20000 ~0xffffffff
64 .b32 #ctx_key + 0xc + 0x20000 ~0xffffffff
65 .b32 #ctx_iv + 0x0 + 0x20000 ~0xffffffff
66 .b32 #ctx_iv + 0x4 + 0x20000 ~0xffffffff
67 .b32 #ctx_iv + 0x8 + 0x20000 ~0xffffffff
68 .b32 #ctx_iv + 0xc + 0x20000 ~0xffffffff
69 .b32 #ctx_src_address_high + 0x20000 ~0xff
70 .b32 #ctx_src_address_low + 0x20000 ~0xfffffff0
71 .b32 #ctx_dst_address_high + 0x20000 ~0xff
72 .b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0
73 .b32 #sec_cmd_mode + 0x00000 ~0xf
74 .b32 #sec_cmd_length + 0x10000 ~0x0ffffff0
75 .equ #engine_cmd_max 0xce
95 .align 0x100
99 	// $r0 is always set to 0 in our code - this allows some space savings.
110 	movw $r1 0xfff0
111 	sethi $r1 0
112 	mov $r2 0x400
113 	iowr I[$r2 + 0x300] $r1
116 	or $r1 0xc
121 	mov $r2 0x1200
136 	iord $r1 I[$r0 + 0x200]
138 	and $r2 $r1 0x8
139 	cmpu b32 $r2 0
143 		mov $r2 0x7700
147 		mov $r2 0
148 		sethi $r2 0x50000
151 		mov $r3 0x1400
155 		cmps b32 $r5 0
162 			bclr $r4 0x1e
166 			iowr I[$r3 + 0x200] $r4
172 			iord $r4 I[$r3 + 0x100]
174 			cmps b32 $r15 0
186 					add b32 $r8 $r6 0x180
195 			iowr I[$r3 + 0x200] $r5
198 	and $r2 $r1 0x4
199 	cmpu b32 $r2 0
203 		mov $r3 0x1900
204 		iord $r2 I[$r3 + 0x100]
207 		and $r4 $r2 0x7ff
209 		shl b32 $r2 0x10
211 		// mthd 0 and 0x100 [NAME, NOP]: ignore
212 		and $r5 $r4 0x7bf
213 		cmpu b32 $r5 0
216 		mov $r5 #engine_cmd_dtable - 0xc0 * 8
218 		cmpu b32 $r4 0xc0
220 		mov $r5 #common_cmd_dtable - 0x80 * 8
222 		cmpu b32 $r4 0x80
224 		cmpu b32 $r4 0x60
226 		cmpu b32 $r4 0x50
229 			// mthd 0x140: PM_TRIGGER
230 			mov $r2 0x2200
232 			sethi $r3 0x20000
237 			// mthd 0x180...: DMA_*
238 			cmpu b32 $r4 0x60+#dma_count
241 			add b32 $r5 ((#ctx_dma - 0x60 * 4) & 0xffff)
242 			bset $r3 0x1e
244 			add b32 $r4 0x180 - 0x60
256 			cmpu b32 $r5 0
279 			mov $r4 0x1000
281 			iowr I[$r4 + 0x100] $r3
282 			mov $r4 0x40
286 				iord $r4 I[$r0 + 0x200]
287 				and $r4 0x40
288 				cmpu b32 $r4 0
293 		mov $r3 0x1d00
299 	and $r1 $r1 0xc
300 	iowr I[$r0 + 0x100] $r1
304 	// if bit 0 of param set, trigger interrupt afterwards.
309 	mov $r4 0xb00
311 		iord $r6 I[$r4 + 0x100]
313 		iord $r7 I[$r4 + 0x100]
319 	st b32 D[$r0 + #swap + 0x0] $r4
320 	st b32 D[$r0 + #swap + 0x4] $r0
321 	st b32 D[$r0 + #swap + 0x8] $r5
322 	st b32 D[$r0 + #swap + 0xc] $r6
324 	// will use target 0, DMA_QUERY.
328 	shl b32 $r4 0x18
333 	sethi $r5 0x20000
362 	and $r6 $r5 0xff
364 	shl b32 $r4 0x18
371 	sethi $r5 0x20000
380 		cmpu b32 $r4 0
387 	add b32 $r6 0x10
388 	add b32 $r5 0x10
393 	ld b32 $r5 D[$r0 + #swap + 0x00]
394 	ld b32 $r6 D[$r0 + #swap + 0x10]
399 	ld b32 $r5 D[$r0 + #swap + 0x04]
400 	ld b32 $r6 D[$r0 + #swap + 0x14]
414 	mov $r2 0x2200
416 	sethi $r3 0x10000
421 	// if >= 0xf, INVALID_ENUM
424 	cmpu b32 $r3 0xf
434 	// nop if length == 0
435 	cmpu b32 $r3 0
441 	sethi $r4 0x70000
444 	sethi $r4 0x60000
450 	mov $r4 0x2100
457 	shl b32 $r4 0x18
459 	and $r5 $r5 0xff
465 	shl b32 $r6 0x18
467 	and $r7 $r7 0xff
482 	cxset 0x61
487 	shr b32 $r8 $r4 0x18
490 	adc b32 $r8 0
495 	shr b32 $r8 $r6 0x18
498 	adc b32 $r8 0
505 	sethi $r4 0x60000
643 	sethi $r9 0x20000
647 		cxset 0x22
651 		add b32 $r5 0x10
662 	sethi $r9 0x20000
665 		cxset 0x61
670 		add b32 $r7 0x10
678 	sethi $r9 0x20000
683 		cxset 0x21
686 		cxset 0x61
692 		add b32 $r5 0x10
693 		add b32 $r7 0x10
698 .align 0x100