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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dmarvell,mpic.yaml58 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
/linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7615/
Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-xp.dtsi35 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
41 reg = <0x1400 0x500>;
46 reg = <0x08000 0x1000>;
47 cache-id-part = <0x100>;
55 pinctrl-0 = <&uart2_pins>;
57 reg = <0x12200 0x100>;
61 clocks = <&coreclk 0>;
67 pinctrl-0 = <&uart3_pins>;
69 reg = <0x12300 0x100>;
73 clocks = <&coreclk 0>;
[all …]
Darmada-xp-98dx3236.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
43 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
44 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
45 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
46 MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
47 MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
51 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
[all …]
Darmada-370.dtsi35 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
47 bus-range = <0x00 0xff>;
50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
57 pcie0: pcie@1,0 {
59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
[all …]
Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
Darmada-375.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
[all …]
Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/linux-6.12.1/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_main.h31 #define HCLGE_INVALID_VPORT 0xffff
37 #define HCLGE_VECTOR_REG_BASE 0x20000
38 #define HCLGE_VECTOR_EXT_REG_BASE 0x30000
39 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
41 #define HCLGE_VECTOR_REG_OFFSET 0x4
42 #define HCLGE_VECTOR_REG_OFFSET_H 0x1000
43 #define HCLGE_VECTOR_VF_OFFSET 0x100000
45 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
48 #define HCLGE_GRO_EN_REG 0x28000
49 #define HCLGE_RXD_ADV_LAYOUT_EN_REG 0x28008
[all …]